T80 cpu

Using the T80a core in a "real-circuit-based" application, I got problems when I activated the part of the circuit using the WAIT_n signal. Analysing the situation with a logic analyser, I found out that the behaviour of the RD_n and WR_n signals during wait cycles externally requested by WAIT_n='0' seems not to be correct. Both signals return to '1' during the wait cycles although an active RD_n or WR_n signal should remain active (='0') during wait cylces according to the Zilog datasheet - this may lead to corrupted memory accesses. To make my application work I slightly modified T80a.vhd. If you are interested, I would be happy to provide the modifications --- just let me know! Best regards and thank you for the great work.