T80 cpu

Problem is simply about inserting WAIT_n in MEM_WR output of Z80.

Need is about having enought time to say to SDRAM : finally I'm not a ROM (@A) but a RAM (@B)... Amstrad CPC 6128 does that : if you write in ROM in fact you write in RAM hidden beside. All that with a poor SDRAM.

A hack is running actually, I add this component with "WAIT_n entry" (just for adding 1 MEM_WR pulse after having detected one MEM_WR rising edge) instead of using Z80 WAIT_n. This component is inserted before clock, and then does not respect Time Contraints at all : library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity please_wait is Port ( CLK_n : in STD_LOGIC; WAIT_n : in STD_LOGIC; CLK_WAIT_n : out STD_LOGIC); end please_wait; architecture Behavioral of please_wait is begin CLK_WAIT_n<=CLK_n or not(WAIT_n); end Behavioral;

In Z80 datasheet, part "Memory Speed Control", you can :

• Figure 21. Adding One Wait State to an M1 Cycle, for slowing memory access about fetching instructions
• Figure 22. Adding One Wait State to Any Memory Cycle, for slowing memory access about MEM WR or RD

In T80.vhd you have : if TState = 2 and Wait_n = '0' then elsif

so if you insert a Wait_n during TState 2, you wait. But this process is under a "CLK_n'event", against T80se.vhd "CLK_n'event"... So the time T80se say me {RD_n,WR_n,IORQ_n,MREQ_n} hello, if I write response, TState is 2 in T80se but TState is 3 in T80.vhd... so I don't reach the thing. Here the first "bug" (minor)... I think that 2 separate components is not a great idea here.

So then I added some constants in T80se in order to insert one/some WAIT_n (in T80.vhd T2) on "MEM_WR", but it does fail (my SDRAM controler is not validated but seems quite ok) Here the second "bug" (major for Amstrad project)

Regards,

Renaud (FPGAmstrad)

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity please_wait is Port ( CLK_n : in STD_LOGIC; WAIT_n : in STD_LOGIC; CLK_WAIT_n : out STD_LOGIC); end please_wait;

architecture Behavioral of please_wait is begin CLK_WAIT_n <=CLK_n or not(WAIT_n); end Behavioral;

For information... In Amstrad a WAIT_n is inserted in order that a MEM_WR does take 24Tstates In Amstrad a WAIT_n is inserted in order that a instruction does take 4TStates (or 24, or 3*4...) in order to synchronize written code with displayed pixel in screen ^^'