T80 cpu

I build a system with t80s and the following generics: mode => 1, -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB t2write => 1, -- 0 => WR_n active in T3, /=0 => WR_n active in T2 iowait => 0, -- 0 => Single cycle I/O, 1 => Std I/O cycle

In context of interrupt observed the following situation in IM2: cycle 0: m1 cycle 1: m1&mreq&rd: read opcode x"db" (in a, (x10)) cycle 2: refresh, int_n becomes 0 cycle 3: refresh cycle 4: cycle 5: mreq&rd: read x"10" from memory (port number) cycle 6+7: cycle 8: iorq&rd: read port x"10" cycle 9: cycle 10: m1 cycle 11: m1&iorq: read index of interrupt vector from IO device cycle 12+13: refresh cycle 14: mreq&refresh ... cycle 22: put address of ISR-table-index to address bus cycle 23: mreq&rd, same address as previous cycle (i. e. cycle 22) It is expected that in cycle 23 the LSBs of the address equals the data value from cycle 11. However, the LSBs of the address are the value of the data bus in cycle 12. In this cycle the IO device does normally not provide the ISR table index.

Workaround: The data bus keeps always its value until a new value is put there.

Note: The reading of the ISR-table-index seem to work in other cases.