T80 cpu

Hi,

I use a t80 core with a Spartan 7 Xilinx FPGA and Vivado for RTL simulation. When fetching a RET (return opcode 0xC9) instruction it should last 10 cycles according to CPU data sheet:

However, when looking at RTL simulation, it last one more cycle (11 instead of 10 as expected):

Is it a know issue ? Could somebody have a look ?

Thanks,

Yann

In fact by using the T80 core from https://github.com/mist-devel/T80 the timing is now ok.