Technologic Systems TS-7300 FPGA Computer

The example usercore contents use all of the headerpins as outputs. If some of the signals are set as inputs (by zeroing some of the bits of headerpin_o_oe), those pins tristate, but the values of headerpin_i are always zero.

This seems to come from ts7300top where the entire pad array is set to zzzzz BEFORE the pad_ values are copied to header_i.