UART16750

Hello,

I have tested you block in a CycloneII (EP2C8T144I8) and I didn't have any interrupt working on receiver. Then I check values of IER and FCR but it seems to be right. Progressing to resolve my problem I see some message on Analysis & synthesis. Here are the messages :

Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(226): object "iFCR" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(234): object "iIER_ERBI" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(235): object "iIER_ETBEI" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(236): object "iIER_ELSI" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(237): object "iIER_EDSSI" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(240): object "iIIR_PI" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(241): object "iIIR_ID0" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(242): object "iIIR_ID1" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(243): object "iIIR_ID2" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(244): object "iIIR_FIFO64" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(306): object "iRInRE" assigned a value but never read

I undrestand why I didn't receive any receiver interrupt... Have you got any idea to correct this ?? Thanks for your answer. Chris.

Hello Chris,

these messages are because the signals listed are not used. They are there because for the sake of completeness.

Interrupts are generated depending on the mode (Non-FIFO, FIFO with different trigger levels, receiver buffer data available timeout).

You can run the testbench with a simulator (Modelsim oder ghdl) and check the interrupt output (or the different interrupt sources in uart_interrupt.vhd).

Have you tried to scope the interrupt output? Does it never changed? It should at least change if no interrupt is pending and you enable the transmitter holding register empty interrupt.

Regards, Sebastian

I forgot to asked how you drive the BAUDCE input (at what rate)?

hi

i have compiled the code using modelsim (uart16750\trunk\rtl\vhdl). but regarding test bench in order to see the wave form result, how to see and use the .do file. i am a beginnner. i have only modelsim tool.

what ever the code given i want to simulate using modelsim tool what step i have to do to see the wave form result.

waiting for response at earliest.

Hey I want know how I can test the ip uart 16750 in interruption. DO you have example in c language ? Cordially.

Hey I want know how I can test the ip uart 16750 in interruption. DO you have example in c language ? Cordially.