UART16750

Hello,

I'm simulating the design using Modelsim Actel 6.6d, but I'm having an undefined value for the SOUT signal.

However, when I verified the internal signal iSOUT, it seems to be correctly. I also verified the signal imcr_loop and it seems to be ok.

Even at the begin of the simulation, when the reset is asserted, the value of iSOUT is undefined.

I think there is a problem with the process UART_OUTREGS in the uart_16750.vhd file.

Thank you,

Regards,

Diego BOTERO diego.botero@hotmail.com