UART16750

Hi Sebastian.

Many thanks for your answer.

I have found my problem using your Quartus project given (for testbench i suppose). I see that you instanciate slib_clock_div with a 18 parameter (a divide by 18 main clock signal to drive BAUDCE) Two things I doesn't understand :

1- What is BAUDCE input ? 2- Why RCLK is connected to BAUDOUTN?

My design have a main clock at 20.48 MHZ and I would like to communicate at 115200 Bauds. At wich rate should I drive BAUDCE ? Could you help me ? Have you got a 'datasheet' or something like ?

Best regards. Chris.

Hi Chris,

BAUDCE is the clock enable input for the baudrate counter. For example, the testbench uses 33 MHz / 18 to get the nearest value to 1.8432 MHz which is used as default clock input for most PC UARTs (so the divider 1 leads to 115200 baud).

You could use 11 to get 1.86 MHz from 20.48 MHz, than a divisor of 1 would be 115200 (more or less).

The formula for the divisor is then:

Divisor = (Frequency generated by clock and BAUDCE) / (Desired baud rate * 16).

(Why do I have to use small comments? If I put all in one it only says "unsuccessfully"....)

Sent you an mail (hope it works).

Did you get it?