UART16750

hello.

the handling of cs/wr/rd seems strange to me. i didn't know if they were high- or lowactive, so i had a look into the sourcecode.

then i stumbled over this: iCSWR <= '1' when CS = '1' and WR = '1' else '0'; iCSRD <= '1' when CS = '1' and RD = '1' else '0'; UART_ED_WRITE: slib_edge_detect port map (CLK => CLK, RST => RST, D => iCSWR, FE => iWriteFE); UART_ED_READ: slib_edge_detect port map (CLK => CLK, RST => RST, D => iCSRD, FE => iReadFE); iWrite <= '1' when iWriteFE = '1' else '0'; iRead <= '1' when iReadFE = '1' else '0';

the way i read this, you are detecting a falling edge on (CS and WR). meaning that when EITHER ONE of them goes low, you have a falling edge. i assume that this is not what you had in mind?

Hello,

yes, that's right. A read or write is also 'finished' when CS goes low and RD or WR is high.

I did not find the expected behaviour in the original datasheets. In the wave diagrams RD/WR goes always low before CS so I would say pulling CS low before RD/WR is out-of-spec...

From the datasheet:

"th3 Hold time, CS valid after WR2 -> low" "th6 Hold time, CS valid after RD2 -> low"

If I understand you correctly than the read/write should be ignored if CS goes low and RD/WR are high?

But what about when CS and RD/WR are going the same time low? Is this a valid end sequence or not? When using the original chip it is not (th3/th6).

Also I think de-asserting CS before RD/WR is finished is pretty uncommon.

Regards, Sebastian