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simulate design in modelsim #5
Closed krishnaprasad_m opened this issue about 14 years ago
krishnaprasad_m commented about 14 years ago

hello,

i want to simulate the design in modelsim tool, how to do, i am a beginner. file given in bench i used but no wave form observed. how to see in modelsim tool. if any notes sort of thing plz upload it, will be very helpful for me to learn.

jjbarrow commented almost 14 years ago

close current transcript file and reopen

transcript file "" transcript file transcript.txt

Simulate with a clean recompile

vdel -lib work -all

Create and new libraries

vlib work vmap work

Compile files into libraries

vcom -work work \ ../../../rtl/vhdl/slib_clock_div.vhd\ ../../../rtl/vhdl/slib_counter.vhd\ ../../../rtl/vhdl/slib_edge_detect.vhd\ ../../../rtl/vhdl/slib_fifo.vhd\ ../../../rtl/vhdl/slib_input_filter.vhd\ ../../../rtl/vhdl/slib_input_sync.vhd\ ../../../rtl/vhdl/slib_mv_filter.vhd\ ../../../rtl/vhdl/uart_baudgen.vhd\ ../../../rtl/vhdl/uart_interrupt.vhd\ ../../../rtl/vhdl/uart_receiver.vhd\ ../../../rtl/vhdl/uart_transmitter.vhd\ ../../../rtl/vhdl/uart_16750.vhd\ ../../../bench/vhdl/txt_util.vhd\ ../../../bench/vhdl/uart_package.vhd\ ../../../bench/vhdl/uart_transactor.vhd\

Start simulator

vsim -t 1ps work.uart_transactor

Before running simulation you must execute the PERL

script in the 'bin' directory to create the file

'uart_stim.dat'

run 1 ps do wave.do

hasw closed this over 5 years ago

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