UART16750

Should DDIS be high on reset not low...?

UART_OUTREGS: process (CLK, RST)
begin
    if (RST = '1') then

-- DDIS <= '0'; --original DDIS <= '1'; --- corrected BAUDOUTN <= '0'; OUT1N <= '0'; OUT2N <= '0'; RTSN <= '0'; DTRN <= '0'; SOUT <= '0'; --elsif (CLK'event and CLK = '1') then elsif rising_edge(CLK) then

Also CLK'Event ... is very old

Yes, thanks. I'll also change the other low-active outputs when RST is asserted.

And CLK'event, well yes rising_edge may be better to read. Have to change my editor macros some day.