FPGA remote slow control via UART 16550
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280--------------------------------------------------------------------- -- Filename: gh_fifo_async16_rcsr_wf.vhd -- -- -- Description: -- a simple Asynchronous FIFO - uses FASM style Memory -- 16 word depth with UART level read flags -- has "Style #2" gray code address compare -- -- Copyright (c) 2007 by Howard LeFevre -- an OpenCores.org Project -- free to use, but see documentation for conditions -- -- Revision History: -- Revision Date Author Comment -- -------- ---------- --------- ----------- -- 1.0 01/20/07 h lefevre Initial revision -- -------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; USE ieee.std_logic_arith.all; entity gh_fifo_async16_rcsr_wf is GENERIC (data_width: INTEGER :=8 ); -- size of data bus port ( clk_WR : in STD_LOGIC; -- write clock clk_RD : in STD_LOGIC; -- read clock rst : in STD_LOGIC; -- resets counters rc_srst : in STD_LOGIC:='0'; -- resets counters (sync with clk_RD!!!) WR : in STD_LOGIC; -- write control RD : in STD_LOGIC; -- read control D : in STD_LOGIC_VECTOR (data_width-1 downto 0); Q : out STD_LOGIC_VECTOR (data_width-1 downto 0); empty : out STD_LOGIC; -- sync with clk_RD!!! q_full : out STD_LOGIC; -- sync with clk_RD!!! h_full : out STD_LOGIC; -- sync with clk_RD!!! a_full : out STD_LOGIC; -- sync with clk_RD!!! full : out STD_LOGIC); end entity; architecture a of gh_fifo_async16_rcsr_wf is component gh_binary2gray IS GENERIC (size: INTEGER := 8); PORT( B : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); G : out STD_LOGIC_VECTOR(size-1 DOWNTO 0) ); end component; component gh_gray2binary IS GENERIC (size: INTEGER := 8); PORT( G : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); -- gray code in B : out STD_LOGIC_VECTOR(size-1 DOWNTO 0) -- binary value out ); end component; type ram_mem_type is array (15 downto 0) of STD_LOGIC_VECTOR (data_width-1 downto 0); signal ram_mem : ram_mem_type; signal iempty : STD_LOGIC; signal diempty : STD_LOGIC; signal ifull : STD_LOGIC; signal add_WR_CE : std_logic; signal add_WR : std_logic_vector(4 downto 0); -- add_width -1 bits are used to address MEM signal add_WR_GC : std_logic_vector(4 downto 0); -- add_width bits are used to compare signal iadd_WR_GC : std_logic_vector(4 downto 0); signal n_add_WR : std_logic_vector(4 downto 0); -- for empty, full flags signal add_WR_RS : std_logic_vector(4 downto 0); -- synced to read clk signal add_RD_CE : std_logic; signal add_RD : std_logic_vector(4 downto 0); signal add_RD_GC : std_logic_vector(4 downto 0); signal iadd_RD_GC : std_logic_vector(4 downto 0); signal add_RD_GCwc : std_logic_vector(4 downto 0); signal iadd_RD_GCwc : std_logic_vector(4 downto 0); signal iiadd_RD_GCwc : std_logic_vector(4 downto 0); signal n_add_RD : std_logic_vector(4 downto 0); signal add_RD_WS : std_logic_vector(4 downto 0); -- synced to write clk signal srst_w : STD_LOGIC; signal isrst_w : STD_LOGIC; signal srst_r : STD_LOGIC; signal isrst_r : STD_LOGIC; signal c_add_RD : std_logic_vector(4 downto 0); signal c_add_WR : std_logic_vector(4 downto 0); signal c_add : std_logic_vector(4 downto 0); begin -------------------------------------------- ------- memory ----------------------------- -------------------------------------------- process (clk_WR) begin if (rising_edge(clk_WR)) then if ((WR = '1') and (ifull = '0')) then ram_mem(CONV_INTEGER(add_WR(3 downto 0))) <= D; end if; end if; end process; Q <= ram_mem(CONV_INTEGER(add_RD(3 downto 0))); ----------------------------------------- ----- Write address counter ------------- ----------------------------------------- add_WR_CE <= '0' when (ifull = '1') else '0' when (WR = '0') else '1'; n_add_WR <= add_WR + "01"; U1 : gh_binary2gray generic map (size => 5) port map( B => n_add_WR, G => iadd_WR_GC ); process (clk_WR,rst) begin if (rst = '1') then add_WR <= (others => '0'); add_RD_WS(4 downto 3) <= "11"; add_RD_WS(2 downto 0) <= (others => '0'); add_WR_GC <= (others => '0'); elsif (rising_edge(clk_WR)) then add_RD_WS <= add_RD_GCwc; if (srst_w = '1') then add_WR <= (others => '0'); add_WR_GC <= (others => '0'); elsif (add_WR_CE = '1') then add_WR <= n_add_WR; add_WR_GC <= iadd_WR_GC; else add_WR <= add_WR; add_WR_GC <= add_WR_GC; end if; end if; end process; full <= ifull; ifull <= '0' when (iempty = '1') else -- just in case add_RD_WS is reset to all zero's '0' when (add_RD_WS /= add_WR_GC) else ---- instend of "11 zero's" '1'; ----------------------------------------- ----- Read address counter -------------- ----------------------------------------- add_RD_CE <= '0' when (iempty = '1') else '0' when (RD = '0') else '1'; n_add_RD <= add_RD + "01"; U2 : gh_binary2gray generic map (size => 5) port map( B => n_add_RD, G => iadd_RD_GC -- to be used for empty flag ); iiadd_RD_GCwc <= (not n_add_RD(4)) & n_add_RD(3 downto 0); U3 : gh_binary2gray generic map (size => 5) port map( B => iiadd_RD_GCwc, G => iadd_RD_GCwc -- to be used for full flag ); process (clk_RD,rst) begin if (rst = '1') then add_RD <= (others => '0'); add_WR_RS <= (others => '0'); add_RD_GC <= (others => '0'); add_RD_GCwc(4 downto 3) <= "11"; add_RD_GCwc(2 downto 0) <= (others => '0'); diempty <= '1'; elsif (rising_edge(clk_RD)) then add_WR_RS <= add_WR_GC; diempty <= iempty; if (srst_r = '1') then add_RD <= (others => '0'); add_RD_GC <= (others => '0'); add_RD_GCwc(4 downto 3) <= "11"; add_RD_GCwc(2 downto 0) <= (others => '0'); elsif (add_RD_CE = '1') then add_RD <= n_add_RD; add_RD_GC <= iadd_RD_GC; add_RD_GCwc <= iadd_RD_GCwc; else add_RD <= add_RD; add_RD_GC <= add_RD_GC; add_RD_GCwc <= add_RD_GCwc; end if; end if; end process; empty <= diempty; iempty <= '1' when (add_WR_RS = add_RD_GC) else '0'; U4 : gh_gray2binary generic map (size => 5) port map( G => add_RD_GC, B => c_add_RD ); U5 : gh_gray2binary generic map (size => 5) port map( G => add_WR_RS, B => c_add_WR ); c_add <= (c_add_WR - c_add_RD); q_full <= '0' when (iempty = '1') else '0' when (c_add(4 downto 2) = "000") else '1'; h_full <= '0' when (iempty = '1') else '0' when (c_add(4 downto 3) = "00") else '1'; a_full <= '0' when (iempty = '1') else '0' when (c_add(4 downto 1) < "0111") else '1'; ---------------------------------- --- sync rest stuff -------------- --- rc_srst is sync with clk_RD -- --- srst_w is sync with clk_WR --- ---------------------------------- process (clk_WR,rst) begin if (rst = '1') then srst_w <= '0'; isrst_r <= '0'; elsif (rising_edge(clk_WR)) then srst_w <= isrst_w; if (srst_w = '1') then isrst_r <= '1'; elsif (srst_w = '0') then isrst_r <= '0'; end if; end if; end process; process (clk_RD,rst) begin if (rst = '1') then srst_r <= '0'; isrst_w <= '0'; elsif (rising_edge(clk_RD)) then srst_r <= rc_srst; if (rc_srst = '1') then isrst_w <= '1'; elsif (isrst_r = '1') then isrst_w <= '0'; end if; end if; end process; end architecture;
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