FPGA remote slow control via UART 16550
Clone Project
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BAUD
PORT
FRAMESIZE
CAPFILE
CAPCOUNT
VISIBLE
DISPLAY
BIGEND
FLOW
EFLOW
RTS
DTR
CLOSED
OPEN
TAB
ECHO
EBAUD
HALF
LFNL
CAPTION
CAPSECS
CAPTURE
CAPQUIT
CAPDIRECT
CAPHEX
TIMESTAMP
CONTROLS
MONITOR
DATA
EDATA
CHARDLY
LINEDLY
ROWS
COLS
SENDFILE
SENDQUIT
SENDDLY
SENDREP
FIRST
SENDSTR
SENDNUM
CR
LF
SPY
SCANPORTS
HELP
I2CADD
SCROLLBACK
COLORS
INSTALL
HEXCSV