Ultimate CRC

I got some trouble with this core when I tried to simulate the parallel module with Modelsim 10.1. Almost all output signal were undefined. My solution: Please add initial values to all signals and variables in the files ucrc_par.vhd and ucrc_ser.vhd. The end of the line can be := (others => '0'); worked for me. Thanks.

If you get undefined output signals you probably have not used the "init" strobe before sending data to the CRC logic. The init strobe will set the CRC register to the INIT_VALUE.

rgds Geir