USB 2.0 Function Core

Hi,

on the bugtracker of USB 2.0 I see two open bugs and I do not see any "succesful story". Has anybody succeeded in using this core ? If yes, with wich FPGAs and PHY devices ?

Thanks,

Tullio

Hi, There is an IEEE paper which has successfully used this design for their experiments on design verification.

https://ieeexplore.ieee.org/document/7435006/references