USB 1.1 PHY

ifdef USB_ASYNC_REST always @(posedge clk or negedge rst)else always @(posedge clk) `endif if(!rst) rx_active <= 1'b0; else if(synced_d && rx_en) rx_active <= 1'b1; else if(se0 && rx_valid_r) rx_active <= 1'b0;

always @(posedge clk) if(rx_valid) rx_valid_r <= 1'b1; else if(fs_ce) rx_valid_r <= 1'b0;

if PHY single end input easier to see 0, it is possible some short "se0" make rx_acive de-asserted, and later packet will loss. Suggest longer SE0(0.75~1.25 bit) before rx_active de-assert.

I think EOP need 2 bits SE0 has its reason. Because differential signal is more easier to be correct, but single-end signal is easier to be jammed/delayed/esd XXX

after modification, the PHY works directly with FPGA IO with much less packet loss.