OpenCores

Viterbi HDL Code Generator

Issue List
converting to k=7 #1
Closed anoopkprabhakaran opened this issue almost 15 years ago
anoopkprabhakaran commented almost 15 years ago

is it posible to edit the code for k=7 rate 1/2 and g0=171 oct ,g1= 133 oct

mike commented almost 15 years ago

yes, put the dec numbers: 121, 91 in the poly option of dialog window, and press generate you can get the RTL code.

mike commented almost 15 years ago

or The CMD version:

perl perl/Oracle.pl -POLYS "121 91" -B 1 -V 1 -RAW 10 -OSR 5 -DBN 2 -SYNCRAM 1

maybe you need adjust the parameters. Good Luck!

mudasir_hussain commented almost 15 years ago

Hello

I am using modelsim 6.5 and have changed the polynomial in the encoder file.vhd of viterbi(1/2 for 9) and parameters respectivly it is encoding perfectly at the rate 1/2 and with polynomial as u have mentioned above for constarain length 7. is it the only change i have to make? or i have chage some parameters in other files also (like decoder e.t.c)and what are they if u can spacify? as i can see that decodedOUT file is not the same as encodeIN one as i only amend the encoder file.vhd .

mike commented almost 15 years ago

What is your polynomial of decoder? You need to regenerate encoder.v, decoder.v, etc,.. if you want to change the polynomial. It looks like the command line:

perl perl/Oracle.pl -POLYS "121 91" -B 1 -V 1 -RAW 10 -OSR 5 -DBN 2 -SYNCRAM 1

It generate Verilog code. If you need VHDL, you need convert them into vhdl using some tools.

Regards,

mudasir_hussain commented almost 15 years ago

Ok tnx for ur quick reply i was actually talking about vhcg_latest.zip download in this zip there is a folder web_uplods and inside this is a k=9_rate=0.5_VHDL folder which has a vhdl code for viterbi. i was talking about this.Now i think i will be clearly understood .Is it so that u have made this viterbi as generic one using verilog and perl stuff and have then converted it for a specific k and rate into Vhdl code? well in encoder file there is a xoring operation that specified the polynomial. i have changed those xor's to 91&121

Regards

mike commented almost 15 years ago

Hi, I generate a decoder of k=7 rate=1/2 (91,121) convolutional code for you. And place them here: https://sourceforge.net/projects/viterbi-gen/files/viterbi-decoder/example/ download poly_91_121_tbdepth_64_VERILOG_VHDL_RTL_TESTBENCH.zip package.

There are VHDL and Verilog RTL code for (91,121) decoder, and testbench. Traceback depth of decoder is 64. Please check the URL I provide, they should contain the information you need.

Regards,

sivabhaskar commented over 14 years ago

Hi every one I am working with xilinx ISE for verilog coding I need viterbi decoder for K=7 rate 1/2 and g0=171 oct ,g1= 133 oct. can i get it how

mike commented over 14 years ago

yes, please input "171 133 " in the poly blank of VHCG's GUI, and generate it.

mike closed this over 14 years ago
nguyentienduy1512 commented almost 10 years ago

How convert verilog to vhdl?


Assignee
No one
Labels
Request