Viterbi Decoder (AXI4-Stream compliant)

The testbench provides blocks of data to the Viterbi decoder with the s_axis_input_tvalid line asserted for the entirety of the block. In other words, the throughput into the decoder is 1 bit (2 symbols)/clock.

If the testbench is modified to provide blocks of data to the Viterbi decoder such that the s_axis_input_tvalid line is only periodically asserted, the decoder does not function and outputs more bits than were input into the decoder. In other words, if the throughput into the decoder is less than 1 bit (2 symbols)/clock, the decoder fails.

Thanks for putting this core together, by the way!

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Note that I think (being a naive person) that the part of the error is in acs.vhd, since m_axis_outdec_tvalid_int is not explicitly set to a '0' if s_axis_inbranch_tvalid is not '1'. However, I am still trying to verify this with the testbench.