Pipelined wishbone to AXI converter

`default_nettype none

Problem with Xilinx Vivado!

The problem is not Xilinx Vivado. I've used default_nettype none many times with Vivado. In this case, though, I haven't defined the inputs are "input wire". Expect an update soon, just not one that will remove thedefault_nettype none.

Thank you for pointing out the problem! I just verified that default_nettype none works with Vivado and this core. Please let me know if you have further problems.

Dan

all good with this one!