Pipelined wishbone to AXI converter

setting ID width to 1 causes synthesis error

This isn't really a bug, but rather a feature. The controller uses the ID width as FIFO id's for outstanding transactions, allowing the transactions to be properly handled on return. A larger ID width allows for a longer/deeper FIFO. A FIFO of one bit would have ... poor performance.

I dug into this some more. The logic within the core will not work properly with an ID width of 1--there are complex issues within the core depending upon the ID width.

well understood, but i tried to minimize resource usage, did set ID width to smallest legit value and got error. if 1 is not valid then it should be indicated that 2 is smallest valid value, etc

You mean like a comment within the core?