OpenCores

Pipelined wishbone to AXI converter

Issue List
reset signal missing #7
Closed antti opened this issue over 6 years ago
antti commented over 6 years ago

reset input is REQUIRED, it should clear the axi master logic, fifos etc etc

dgisselq was assigned over 6 years ago
dgisselq commented over 6 years ago

A synchronous reset has been added, and now verified. It is a positive logic reset, though, and not one with negative logic.

dgisselq closed this over 6 years ago
antti commented over 6 years ago

hi good, but positive logic means unfortunatly that for vivado a there is a need for a dummy wrapper that inverts reset logic :(

dgisselq commented over 6 years ago

Would a parameter controlling which type of reset was used meet your purpose?


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dgisselq
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