Wishbone LPC Host and Peripheral Bridge
LPC Peripheral illegaly drives the bus during TAR #6
Open danielpreda opened this issue over 16 years ago
danielpreda commented over 16 years ago
The host finishes the first part of TAR. It should follow another cycle of 4'b1111, when no one drives the bus. But the peripheral immediately starts driving the SYNC.
hharte was assigned over 16 years ago
hharte commented over 16 years ago
I believe this bug occurs if the host drives LFRAME# for more than one cycle. The spec allows LFRAME# to be driven for more than one cycle, so this is a bug in the peripheral.
© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.