Wishbone LPC Host and Peripheral Bridge

Quartus v8.1 is unable to synthesize wb_lpc_periph.v.

It gives the following error (for each lpc_dat_i bit): Error (10818): Can't infer register for "lpc_dat_i0" at wb_lpc_periph.v(419) because it does not hold its value outside the clock edge

This looks like a Quartus problem, rather than a coding problem!?!

The solution is to move: lpc_dat_i <= 32'h00000000; from the 1st if(~nrst_i) statement (~line 120) into the 2nd (~line 390).

FWIW I actually tried splitting the two 'if' statements into 2 separate 'always' blocks, and got 'unable to resolve multiple drivers for lpc_dat_i'. The above change fixed that problem, and subsequently re-merging back into a single 'always' block worked - well, synthesized - as well.