Another Wishbone Controlled UART

Even Parity Error (Maybe All Parity) #1

Open NickX opened this issue over 2 years ago

Hello ! I want to talk about error for even parity control (maybe all parity control) to transmitting info. In you're test not use parity control.

Parity calculated with:

https://www.electronicshub.org/error-correction-and-detection-codes/#_Parity_Checking

and

https://www.dlsweb.rmit.edu.au/set/Courses/Content/CSIT/oua/cpt160/2014sp4/chapter/05/ErrorDetectionandCorrection.html

and

https://ru.wikipedia.org/wiki/%D0%A3%D0%BD%D0%B8%D0%B2%D0%B5%D1%80%D1%81%D0%B0%D0%BB%D1%8C%D0%BD%D1%8B%D0%B9%D0%B0%D1%81%D0%B8%D0%BD%D1%85%D1%80%D0%BE%D0%BD%D0%BD%D1%8B%D0%B9%D0%BF%D1%80%D0%B8%D1%91%D0%BC%D0%BE%D0%BF%D0%B5%D1%80%D0%B5%D0%B4%D0%B0%D1%82%D1%87%D0%B8%D0%BA#%D0%9A%D0%BE%D0%BD%D1%82%D1%80%D0%BE%D0%BB%D1%8C_%D1%87%D1%91%D1%82%D0%BD%D0%BE%D1%81%D1%82%D0%B8

For exapmle:

Data = 00000000 Numbers of "1" = 0 Even Parity = 0 Odd Parity = 1 Data = 01010001 Numbers of "1" = 3 Even Parity = 1 Odd Parity = 0 Data = 01101001 Numbers of "1" = 4 Even Parity = 0 Odd Parity = 1 Data = 01111111 Numbers of "1" = 7 Even Parity = 1 Odd Parity = 0

Please check all parity in module

In diagram to this test, transmitter use Odd parity, but parity in parameter is Even.

To checking error you can use my test:

// Copyright (C) 1991-2009 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details.

// * // This file contains a Verilog test bench template that is freely editable to
// suit user's needs .Comments are provided in each section to help the user
// fill out necessary details.
// * // Generated on "06/30/2021 10:36:20"

// Verilog Test Bench template for design : WorkPlaceCodec // // Simulation tool : ModelSim-Altera (Verilog) //

`timescale 1 ns/ 1 ps module wbuart_test;

// constants
// general purpose registers reg eachvec;

// BASE INPUT FREQUENCE //--------------------------------------------------- reg CLK_49_152; //---------------------------------------------------

// UART FREQUENCE //--------------------------------------------------- reg CLK_115_200; //---------------------------------------------------

//REG FOR WBUART //---------------------------------------------------

integer parity_on_off = 1; //(PARITY ON) integer parity_type = 1; //(EVEN) integer OneTwoStopBits = 2; //(TWO STOP BIT)

// test vector input registers //reg CLK_49_152; reg RESET; reg I_WB_CYC; reg I_WB_STB; reg I_WB_WE; reg 1:0 I_WB_ADDR; reg 31:0 I_WB_DATA; reg I_UART_RX; reg I_CTS_N;

wire O_WB_ACK; wire O_WB_STALL; wire 31:0 O_WB_DATA; wire O_UART_TX; wire O_RTS_N; wire O_UART_RX_INT; wire O_UART_TX_INT; wire O_UART_RXFIFO_INT; wire O_UART_TXFIFO_INT; //------------------------------------------------------------

// CREATE OBJECT - WBUART //------------------------------------------------------------

//Parameters on register:

//BaudRate (bod per sec): 115 200 //Data Bits: 8 bits //Parity: Even //Stop Bits: 2 (Two Stop Bits) //Flow Control: NoFlowControl //Input Frequence: 49.152 MHz

defparam i2.INITIAL_SETUP = 31'b0001101000000000000000110101011; defparam i2.LGFLEN = 10; defparam i2.HARDWARE_FLOW_CONTROL_PRESENT = 1'b1;

// assign statements (if any)
wbuart i2 (
// port map - connection between master ports and signals/registers .i_clk(CLK_49_152), .i_rst(RESET), .i_wb_cyc(I_WB_CYC), .i_wb_stb(I_WB_STB), .i_wb_we(I_WB_WE), .i_wb_addr(I_WB_ADDR), .i_wb_data(I_WB_DATA), .i_uart_rx(I_UART_RX), .i_cts_n(I_CTS_N),

.o_wb_ack(O_WB_ACK), .o_wb_stall(O_WB_STALL), .o_wb_data(O_WB_DATA), .o_uart_tx(O_UART_TX), .o_rts_n(O_RTS_N), .o_uart_rx_int(O_UART_RX_INT), .o_uart_tx_int(O_UART_TX_INT), .o_uart_rxfifo_int(O_UART_RXFIFO_INT), .o_uart_txfifo_int(O_UART_TXFIFO_INT) ); //------------------------------------------------------------

//This block generated base Frequence by generator 49,152 MHz //-----------------------------------------------------------

always
// optional sensitivity list
// @(event1 or event2 or .... eventn)
begin
// code executes for every event on sensitivity list
// insert code here --> begin

//Every 10.1725 ns => 49.152 Mhz = 1/(49.152210^(6)) = 0.01017252604167*(10^(-6)) #10.17252604167 CLK_49_152 = ~CLK_49_152;

//@eachvec;
// --> end
end

//This block generated Frequence by UART 115200 bod/s //-----------------------------------------------------------

always
// optional sensitivity list
// @(event1 or event2 or .... eventn)
begin
// code executes for every event on sensitivity list
// insert code here --> begin

//Every 4.3402777777777777 ns => 115 200 Hz = 1/(1152002) = 4.3402777777777777(10^(-6)) #4340.2777777777777777 CLK_115_200 = ~CLK_115_200; //#8680.55555555555555 CLK_115_200 = ~CLK_115_200; //#17361.111111111111111 CLK_115_200 = ~CLK_115_200;

//@eachvec;
// --> end
end

//----------------------------------------------------------

initial
begin
// code that executes only once
// insert code here --> begin

CLK_49_152 = 0; CLK_115_200 = 0;

begin

//This signal always have this values //UART work always I_WB_CYC = 0; I_WB_STB = 1;

//FOR UART

I_WB_ADDR = 2'b0; I_WB_WE = 0; I_WB_DATA = 32'b0; I_UART_RX = 1; I_CTS_N = 0;

end

#100 //pause

// --> end
$display("Running testbench");
#100 //pause

// --> end
$display("Running testbench");

// TEST FOR WBUART //----------------------------------------------------------

//RESET_ALL

@(posedge CLK_49_152) // begin RESET = 1; end

@(posedge CLK_49_152) // begin RESET = 0; end

// TEST WBUART //---------------------------------------------------------

#250000

//WORK

//Send Command to set MODE

send_ls_byte(8'b10101010, OneTwoStopBits, parity_on_off, parity_type); //Header #250000 send_ls_byte(8'd6, OneTwoStopBits, parity_on_off, parity_type); //Lenght Command #250000 send_ls_byte(8'd1, OneTwoStopBits, parity_on_off, parity_type); //Command for Loop #250000 send_ls_byte(8'd3, OneTwoStopBits, parity_on_off, parity_type); //Code of doing #250000 send_ls_byte(8'd1, OneTwoStopBits, parity_on_off, parity_type); //Number of MODE #250000 send_ls_byte(8'b10101010, OneTwoStopBits, parity_on_off, parity_type); //Footer

#250000 #250000

//Send Command to read MODE send_ls_byte(8'b10101010, OneTwoStopBits, parity_on_off, parity_type); //Header //#250000 send_ls_byte(8'd5, OneTwoStopBits, parity_on_off, parity_type); //Lenght Command //#250000 send_ls_byte(8'd1, OneTwoStopBits, parity_on_off, parity_type); //Command for Loop //#250000 send_ls_byte(8'd0, OneTwoStopBits, parity_on_off, parity_type); //Code of doing //#250000 send_ls_byte(8'b10101010, OneTwoStopBits, parity_on_off, parity_type); //Footer //#250000

#250000 #250000

//Send Command to Transmit to interface PS send_ls_byte(8'b10101010, OneTwoStopBits, parity_on_off, parity_type); //Header #250000 send_ls_byte(8'd8, OneTwoStopBits, parity_on_off, parity_type); //Lenght Command #250000 send_ls_byte(8'd1, OneTwoStopBits, parity_on_off, parity_type); //Command for Loop #250000 send_ls_byte(8'd0, OneTwoStopBits, parity_on_off, parity_type); //Code of doing #250000 send_ls_byte(8'd1, OneTwoStopBits, parity_on_off, parity_type); //Adress of device #250000 send_ls_byte(8'b00110011, OneTwoStopBits, parity_on_off, parity_type); //Byte 1 of command to device #250000 send_ls_byte(8'b00001111, OneTwoStopBits, parity_on_off, parity_type); //Byte 2 of command to device #250000 send_ls_byte(8'b10101010, OneTwoStopBits, parity_on_off, parity_type); //Footer

/**/

#250000

//Real From RX-FIFO

@(posedge CLK_49_152) // begin I_WB_ADDR = 2'b10; end

@(posedge CLK_49_152) // begin I_WB_ADDR = 2'b00; end

#250000 #250000

//Transmit bytes

@(posedge CLK_49_152) // begin transmit_ls_byte(8'b10101010); end

#250000

@(posedge CLK_49_152) // begin transmit_ls_byte(8'd6); end

#250000

@(posedge CLK_49_152) // begin transmit_ls_byte(8'd1); end

#250000

@(posedge CLK_49_152) // begin transmit_ls_byte(8'd3); end

#250000

@(posedge CLK_49_152) // begin transmit_ls_byte(8'd1); end

#250000

@(posedge CLK_49_152) // begin transmit_ls_byte(8'b10101010); end

#250000 #250000

@(posedge CLK_49_152) // begin transmit_ls_byte(8'b10101010); end

@(posedge CLK_49_152) // begin transmit_ls_byte(8'd5); end

@(posedge CLK_49_152) // begin transmit_ls_byte(8'd1); end

@(posedge CLK_49_152) // begin transmit_ls_byte(8'd0); end

@(posedge CLK_49_152) // begin transmit_ls_byte(8'b10101010); end #250000

#250000 #250000 #250000

@(posedge CLK_49_152) // begin transmit_ls_byte(8'b10101010); end

#250000

@(posedge CLK_49_152) // begin transmit_ls_byte(8'd8); end

#250000

@(posedge CLK_49_152) // begin transmit_ls_byte(8'd1); end

#250000

@(posedge CLK_49_152) // begin transmit_ls_byte(8'd0); end

#250000

@(posedge CLK_49_152) // begin transmit_ls_byte(8'b00110011); end

#250000

@(posedge CLK_49_152) // begin transmit_ls_byte(8'b00001111); end

#250000

@(posedge CLK_49_152) // begin transmit_ls_byte(8'b10101010); end

#250000 #250000 #250000

@(posedge CLK_49_152) // begin transmit_ls_byte(8'b00000000); end

#250000

@(posedge CLK_49_152) // begin transmit_ls_byte(8'b01010001); end

#250000

@(posedge CLK_49_152) // begin transmit_ls_byte(8'b01101001); end

#250000

@(posedge CLK_49_152) // begin transmit_ls_byte(8'b01111111); end

#250000

@(posedge CLK_49_152) // begin transmit_ls_byte(8'h30); end

/ @(posedge CLK_49_152) // begin DATA_P = 16'b0000111100001111; ADRESS = 0; WR_DATE_ADRESS = 1; end /

//----------------------------------------------------------

//#10000

//end

end

//Transmit byte to UART //parity_on_off == 1 - parity ON //parity_on_off == 0 - parity OFF

//parity_type == 1 - EVEN parity //parity_type == 0 - ODD parity

//OneTwoStopBits == 0 - One Stop Bit //OneTwoStopBits == 1 - Two Stop Bit

task send_ls_byte(input 7:0sbyte, input integer OneTwoStopBits, input integer parity_on_off, input integer parity_type); integer i; integer p; begin

p = 0; //Calculate Parity for(i=0; i<8; i=i+1) begin if (sbytei == 1) begin p = p + 1; end end

//Start bit @(posedge CLK_115_200) begin I_UART_RX = 0; end

//Transmit bit per bit (Little bit Forever) for(i=0; i<8; i=i+1) begin @(posedge CLK_115_200) begin I_UART_RX = sbytei; end end

if (parity_on_off == 1) begin

 //Parity Even: 001110110 => parity_bit=1 numbers of "1" in data bits = 5 - no parity number
 //Parity Even: 101110110 => parity_bit=0 numbers of "1" in data bits = 6 - parity number or = 0
 if (parity_type == 1) begin        
   if ((p%2 == 0)||(p == 0)) begin
     @(posedge CLK_115_200)
     begin
     I_UART_RX = 0;
     end 
   end else begin
     @(posedge CLK_115_200)
     begin
     I_UART_RX = 1;
     end
   end
 end
 
 //Parity Odd: 001110110 => parity_bit=0 numbers of "1" in data bits = 5 - no parity number or = 0
 //Parity Odd: 101110110 => parity_bit=1 numbers of "1" in data bits = 6 - parity number     
 if (parity_type == 0) begin // Odd
   if ((p%2 == 0)&&(p != 0)) begin
     @(posedge CLK_115_200)
     begin
     I_UART_RX = 1;
     end 
   end else begin
     @(posedge CLK_115_200)
     begin
     I_UART_RX = 0;
     end
   end
 end
 
 //One Stop Bit (first stop bit must be)
 @(posedge CLK_115_200)
 begin
 I_UART_RX = 1;
 end
 
 //Two Stop Bit (optional: if two stop bit is)
 if (OneTwoStopBits == 2) begin
 @(posedge CLK_115_200)
 begin
 I_UART_RX = 1;
 end
 end

end else begin

//One Stop Bit and all (first stop bit must be) @(posedge CLK_115_200) begin I_UART_RX = 1; end

//Two Stop Bit (optional: if two stop bit is) if (OneTwoStopBits == 2) begin @(posedge CLK_115_200) begin I_UART_RX = 1; end end

end

//Return Line to log 1 @(posedge CLK_115_200) begin I_UART_RX = 1; end

end endtask

task transmit_ls_byte(input 7:0sbyte); integer i; integer p; begin

p = 0;

//Start @(posedge CLK_49_152) begin I_WB_ADDR = 2'b11; I_WB_WE = 1; I_WB_DATA = sbyte; end

//Stop @(posedge CLK_49_152) begin I_WB_ADDR = 2'b00; I_WB_WE = 0; I_WB_DATA = sbyte; end

end endtask

endmodule

Please check this or if I don't right contact me to nshushakov777@gmail.com

P.S. Sorry, I bed speak English.

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