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Written in:
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VHDL
Verilog & VHDL
Verilog
SystemC
Bluespec
C/C++
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Stage:
Any stage
Planning
Mature
Alpha
Beta
Stable
License:
Any license
GPL
LGPL
BSD
CERN-OHL-S
CERN-OHL-L
CERN-OHL2-P
Others
Wishbone version:
Any version
B.3
B.4
ASIC proven
Design done
FPGA proven
Specification done
OpenCores Certified
Arithmetic core
2
Communication controller
4
Crypto core
1
ECC core
1
Library
1
Other
1
Processor
9
System on Chip
1
Testing / Verification
2
Video controller
2
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