Username:
Password:
Remember me
Register
Browse
Projects
Forums
About
Mission
Logos
Community
Statistics
HowTo/FAQ
FAQ
Project
SVN
WISHBONE
EDA Tools
Media
News
Articles
Newsletter
Licensing
Commerce
Shop
Advertise
Jobs
Partners
Maintainers
Contact us
Written in:
Any language
VHDL
Verilog & VHDL
Verilog
SystemC
Bluespec
C/C++
Other
Stage:
Any stage
Planning
Mature
Alpha
Beta
Stable
License:
Any license
GPL
LGPL
BSD
CERN-OHL-S
CERN-OHL-L
CERN-OHL2-P
Others
Wishbone version:
Any version
B.3
B.4
ASIC proven
Design done
FPGA proven
Specification done
OpenCores Certified
Arithmetic core
119
Prototype board
42
Communication controller
221
Coprocessor
11
Crypto core
81
DSP core
49
ECC core
24
Library
21
Memory core
51
Other
120
Processor
227
System on Chip
86
System on Module
2
System controller
21
Testing / Verification
37
Video controller
50
Uncategorized
94
© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.