Written in:Any languageVHDLVerilog & VHDLVerilogSystemCBluespecC/C++Other

Stage:Any stagePlanningMatureAlphaBetaStable

License:Any licenseGPLLGPLBSDCERN-OHL-SCERN-OHL-LCERN-OHL2-POthers

Wishbone version:Any versionB.3B.4

ASIC proven

Design done

FPGA proven

Specification done

OpenCores Certified

Arithmetic core 120

Prototype board 43

Communication controller 222

Coprocessor 13

Project	Files	Statistics	Status	License	Wishbone version
CF Reconfigurable Computing Array		Stats
CPU Code Execution Timestamp		Stats		LGPL
Fixed-Point 32-bit Convolution Architecture		Stats		LGPL
FlexGripPlus General Purpose Graphics Processing Unit (GPGPU) core		Stats		LGPL
Floating Point Unit		Stats
JT51 - YM2151 compatible core		Stats		GPL
Neutal Net Perceptron for Pattern Recognition		Stats		GPL	B.4
ORSoC Graphics Accelerator		Stats		LGPL
Reconfigurable, Power-Aware 4×4 Tensor Core for Sparse Mixed-Precision Matrix Processing		Stats		LGPL
Stereo Vision Core		Stats		LGPL
USB 2.0 capture and decode core		Stats		LGPL
xgate		Stats		LGPL
ztachip		Stats		LGPL

Crypto core 81

DSP core 49

ECC core 25

Library 21

Memory core 52

Other 124

Processor 227

System on Chip 87

System on Module 2

System controller 21

Testing / Verification 38

Video controller 50

Uncategorized 95