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Written in:
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VHDL
Verilog & VHDL
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Stage:
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License:
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CERN-OHL-S
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Wishbone version:
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B.3
B.4
ASIC proven
Design done
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Specification done
OpenCores Certified
Arithmetic core
53
Prototype board
8
Communication controller
89
Coprocessor
4
Crypto core
44
DSP core
24
ECC core
9
Library
12
Memory core
16
Other
50
Processor
93
System on Chip
33
System controller
9
Testing / Verification
13
Video controller
20
Uncategorized
7
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