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Written in:
Any language
VHDL
Verilog & VHDL
Verilog
SystemC
Bluespec
C/C++
Other
Stage:
Any stage
Planning
Mature
Alpha
Beta
Stable
License:
Any license
GPL
LGPL
BSD
CERN-OHL-S
CERN-OHL-L
CERN-OHL2-P
Others
Wishbone version:
Any version
B.3
B.4
ASIC proven
Design done
FPGA proven
Specification done
OpenCores Certified
Arithmetic core
19
Prototype board
6
Communication controller
33
Coprocessor
3
Crypto core
20
DSP core
6
ECC core
3
Library
3
Memory core
8
Other
24
Processor
42
System on Chip
12
System controller
3
Testing / Verification
5
Video controller
9
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