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Written in:
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VHDL
Verilog & VHDL
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Mature
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License:
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CERN-OHL-S
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Wishbone version:
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B.3
B.4
ASIC proven
Design done
FPGA proven
Specification done
OpenCores Certified
Arithmetic core
26
Prototype board
3
Communication controller
28
Coprocessor
1
Crypto core
11
DSP core
6
ECC core
2
Library
3
Memory core
4
Other
17
Processor
40
System on Chip
16
System controller
7
Testing / Verification
8
Video controller
7
Uncategorized
2
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