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[/] [1000base-x/] [trunk/] [rtl/] [verilog/] [clean_rst.v] - Blame information for rev 3

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1 3 dwp
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  File name "clean_rst.v"                                     ////
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////                                                              ////
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////  This file is part of the :                                  ////
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////                                                              ////
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//// "1000BASE-X IEEE 802.3-2008 Clause 36 - PCS project"         ////
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////                                                              ////
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////  http://opencores.org/project,1000base-x                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - D.W.Pegler Cambridge Broadband Networks Ltd           ////
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////                                                              ////
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////      { peglerd@gmail.com, dwp@cambridgebroadand.com }        ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 AUTHORS. All rights reserved.             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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module clean_rst(
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  input      clk,
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  input      rsti,
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  output reg rsto
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);
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  reg rstt;
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   always @(posedge clk, posedge rsti)
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     begin
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        rstt <= (rsti) ? 1 : 0;
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        rsto <= (rsti) ? 1 : rstt;
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     end
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endmodule
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