1 |
3 |
dwp |
//////////////////////////////////////////////////////////////////////
|
2 |
|
|
//// ////
|
3 |
|
|
//// File name "decoder_8b10b.v" ////
|
4 |
|
|
//// ////
|
5 |
|
|
//// This file is part of the : ////
|
6 |
|
|
//// ////
|
7 |
|
|
//// "1000BASE-X IEEE 802.3-2008 Clause 36 - PCS project" ////
|
8 |
|
|
//// ////
|
9 |
|
|
//// http://opencores.org/project,1000base-x ////
|
10 |
|
|
//// ////
|
11 |
|
|
//// Author(s): ////
|
12 |
|
|
//// - D.W.Pegler Cambridge Broadband Networks Ltd ////
|
13 |
|
|
//// ////
|
14 |
|
|
//// { peglerd@gmail.com, dwp@cambridgebroadand.com } ////
|
15 |
|
|
//// ////
|
16 |
|
|
//////////////////////////////////////////////////////////////////////
|
17 |
|
|
//// ////
|
18 |
|
|
//// Copyright (C) 2009 AUTHORS. All rights reserved. ////
|
19 |
|
|
//// ////
|
20 |
|
|
//// This source file may be used and distributed without ////
|
21 |
|
|
//// restriction provided that this copyright statement is not ////
|
22 |
|
|
//// removed from the file and that any derivative work contains ////
|
23 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
24 |
|
|
//// ////
|
25 |
|
|
//// This source file is free software; you can redistribute it ////
|
26 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
27 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
28 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
29 |
|
|
//// later version. ////
|
30 |
|
|
//// ////
|
31 |
|
|
//// This source is distributed in the hope that it will be ////
|
32 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
33 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
34 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
35 |
|
|
//// details. ////
|
36 |
|
|
//// ////
|
37 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
38 |
|
|
//// Public License along with this source; if not, download it ////
|
39 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
40 |
|
|
//// ////
|
41 |
|
|
//////////////////////////////////////////////////////////////////////
|
42 |
|
|
//// ////
|
43 |
|
|
//// This module is based on the coding method described in ////
|
44 |
|
|
//// IEEE Std 802.3-2008 Section 36.2.4 which is available from : ////
|
45 |
|
|
//// ////
|
46 |
|
|
//// http://standards.ieee.org/about/get/802/802.3.html ////
|
47 |
|
|
//// ////
|
48 |
|
|
//// and the 8B/10B coding scheme from the 1993 IBM publication ////
|
49 |
|
|
//// "DC-Balanced, Partitioned-Block, 8B/10B Transmission Code" ////
|
50 |
|
|
//// by A.X. Widmer and P.A. Franasze" see doc/01-581v1.pdf ////
|
51 |
|
|
//// ////
|
52 |
|
|
//// and US patent #4,486,739 "BYTE ORIENTED DC BALANCED ////
|
53 |
|
|
//// (0,4) 8B/10B PARTITIONED BLOCK TRANSMISSION CODE "; see : ////
|
54 |
|
|
//// ////
|
55 |
|
|
//// doc/US4486739.pdf ////
|
56 |
|
|
//// ////
|
57 |
|
|
//// http://en.wikipedia.org/wiki/8b/10b_encoding ////
|
58 |
|
|
//// ////
|
59 |
|
|
//////////////////////////////////////////////////////////////////////
|
60 |
|
|
|
61 |
|
|
|
62 |
|
|
`include "timescale.v"
|
63 |
|
|
|
64 |
|
|
module decoder_8b10b (
|
65 |
|
|
|
66 |
|
|
// --- Resets ---
|
67 |
|
|
input reset,
|
68 |
|
|
|
69 |
|
|
// --- Clocks ---
|
70 |
|
|
input RBYTECLK,
|
71 |
|
|
|
72 |
|
|
// --- TBI (Ten Bit Interface) input bus
|
73 |
|
|
input [9:0] tbi,
|
74 |
|
|
|
75 |
|
|
// --- Control (K)
|
76 |
|
|
output reg K_out,
|
77 |
|
|
|
78 |
|
|
// -- Eight bit output bus
|
79 |
|
|
output reg [7:0] ebi,
|
80 |
|
|
|
81 |
|
|
// --- 8B/10B RX coding error ---
|
82 |
|
|
output reg coding_err,
|
83 |
|
|
|
84 |
|
|
// --- 8B/10B RX disparity ---
|
85 |
|
|
output reg disparity,
|
86 |
|
|
|
87 |
|
|
// --- 8B/10B RX disparity error ---
|
88 |
|
|
output disparity_err
|
89 |
|
|
|
90 |
|
|
);
|
91 |
|
|
|
92 |
|
|
`ifdef MODEL_TECH
|
93 |
|
|
// ModelSim debugging only
|
94 |
|
|
wire [4:0] decoder_8b_X; wire [2:0] decoder_8b_Y;
|
95 |
|
|
|
96 |
|
|
assign decoder_8b_X = ebi[4:0];
|
97 |
|
|
assign decoder_8b_Y = ebi[7:5];
|
98 |
|
|
`endif
|
99 |
|
|
|
100 |
|
|
wire a,b,c,d,e,i,f,g,h,j; // 10 Bit inputs
|
101 |
|
|
|
102 |
|
|
assign {a,b,c,d,e,i,f,g,h,j} = tbi[9:0];
|
103 |
|
|
|
104 |
|
|
// ******************************************************************************
|
105 |
|
|
// Figure 10 - Decoder: 6b - Signals
|
106 |
|
|
// ******************************************************************************
|
107 |
|
|
wire AEQB, CEQD, P22, P13, P31;
|
108 |
|
|
|
109 |
|
|
// ******************************************************************************
|
110 |
|
|
// Figure 11 - Decoder: K - Signals
|
111 |
|
|
// ******************************************************************************
|
112 |
|
|
|
113 |
|
|
wire eeqi, c_d_e_i, cn_dn_en_in;
|
114 |
|
|
|
115 |
|
|
wire P22_a_c_eeqi, P22_an_cn_eeqi;
|
116 |
|
|
|
117 |
|
|
wire P22_b_c_eeqi, P22_bn_cn_eeqi, an_bn_en_in;
|
118 |
|
|
|
119 |
|
|
wire a_b_e_i, P13_d_e_i, P13_in, P13_en, P31_i;
|
120 |
|
|
|
121 |
|
|
// ******************************************************************************
|
122 |
|
|
// Figure 12 - Decoder: 5B - Signals
|
123 |
|
|
// ******************************************************************************
|
124 |
|
|
|
125 |
|
|
wire OR12_1, OR12_2, OR12_3, OR12_4, OR12_5, OR12_6, OR12_7;
|
126 |
|
|
|
127 |
|
|
wire A, B, C, D, E;
|
128 |
|
|
|
129 |
|
|
// ******************************************************************************
|
130 |
|
|
// Figure 13 - Decoder: 3B - Signals
|
131 |
|
|
// ******************************************************************************
|
132 |
|
|
|
133 |
|
|
wire K, F, G, H, K28p, KA, KB, KC;
|
134 |
|
|
|
135 |
|
|
// ******************************************************************************
|
136 |
|
|
// Figure 10 - Decoder: 6b Input Function
|
137 |
|
|
// ******************************************************************************
|
138 |
|
|
|
139 |
|
|
assign AEQB = (a & b) | (!a & !b) ;
|
140 |
|
|
assign CEQD = (c & d) | (!c & !d) ;
|
141 |
|
|
assign P22 = (a & b & !c & !d) | (c & d & !a & !b) | ( !AEQB & !CEQD) ;
|
142 |
|
|
assign P13 = ( !AEQB & !c & !d) | ( !CEQD & !a & !b) ;
|
143 |
|
|
assign P31 = ( !AEQB & c & d) | ( !CEQD & a & b) ;
|
144 |
|
|
|
145 |
|
|
// ******************************************************************************
|
146 |
|
|
// Figure 11 - Decoder: K
|
147 |
|
|
// ******************************************************************************
|
148 |
|
|
|
149 |
|
|
assign eeqi = (e == i);
|
150 |
|
|
|
151 |
|
|
assign P22_a_c_eeqi = P22 & a & c & eeqi;
|
152 |
|
|
assign P22_an_cn_eeqi = P22 & !a & !c & eeqi;
|
153 |
|
|
|
154 |
|
|
assign cn_dn_en_in = (!c & !d & !e & !i);
|
155 |
|
|
assign c_d_e_i = (c & d & e & i);
|
156 |
|
|
|
157 |
|
|
assign KA = c_d_e_i | cn_dn_en_in;
|
158 |
|
|
assign KB = P13 & (!e & i & g & h & j);
|
159 |
|
|
assign KC = P31 & (e & !i & !g & !h & !j);
|
160 |
|
|
|
161 |
|
|
assign K = KA | KB | KC;
|
162 |
|
|
|
163 |
|
|
assign P22_b_c_eeqi = P22 & b & c & eeqi;
|
164 |
|
|
assign P22_bn_cn_eeqi = P22 & !b & !c & eeqi;
|
165 |
|
|
assign an_bn_en_in = !a & !b & !e & !i;
|
166 |
|
|
assign a_b_e_i = a & b & e & i;
|
167 |
|
|
assign P13_d_e_i = P13 & d & e & i;
|
168 |
|
|
assign P13_in = P13 & !i;
|
169 |
|
|
assign P13_en = P13 & !e;
|
170 |
|
|
assign P31_i = P31 & i;
|
171 |
|
|
|
172 |
|
|
|
173 |
|
|
// ******************************************************************************
|
174 |
|
|
// Figure 12 - Decoder: 5B/6B
|
175 |
|
|
// ******************************************************************************
|
176 |
|
|
|
177 |
|
|
assign OR12_1 = P22_an_cn_eeqi | P13_en;
|
178 |
|
|
assign OR12_2 = a_b_e_i | cn_dn_en_in | P31_i;
|
179 |
|
|
assign OR12_3 = P31_i | P22_b_c_eeqi | P13_d_e_i;
|
180 |
|
|
assign OR12_4 = P22_a_c_eeqi | P13_en;
|
181 |
|
|
assign OR12_5 = P13_en | cn_dn_en_in | an_bn_en_in;
|
182 |
|
|
assign OR12_6 = P22_an_cn_eeqi | P13_in;
|
183 |
|
|
assign OR12_7 = P13_d_e_i | P22_bn_cn_eeqi;
|
184 |
|
|
|
185 |
|
|
assign A = a ^ (OR12_7 | OR12_1 | OR12_2);
|
186 |
|
|
assign B = b ^ (OR12_2 | OR12_3 | OR12_4);
|
187 |
|
|
assign C = c ^ (OR12_1 | OR12_3 | OR12_5);
|
188 |
|
|
assign D = d ^ (OR12_2 | OR12_4 | OR12_7);
|
189 |
|
|
assign E = e ^ (OR12_5 | OR12_6 | OR12_7);
|
190 |
|
|
|
191 |
|
|
// ******************************************************************************
|
192 |
|
|
// Figure 13 - Decoder: 3B/4B
|
193 |
|
|
// ******************************************************************************
|
194 |
|
|
|
195 |
|
|
// K28 with positive disp into fghi - .1, .2, .5, and .6 specal cases
|
196 |
|
|
assign K28p = ! (c | d | e | i) ;
|
197 |
|
|
|
198 |
|
|
assign F = (j & !f & (h | !g | K28p)) | (f & !j & (!h | g | !K28p)) | (K28p & g & h) | (!K28p & !g & !h) ;
|
199 |
|
|
|
200 |
|
|
assign G = (j & !f & (h | !g | !K28p)) | (f & !j & (!h | g |K28p)) | (!K28p & g & h) | (K28p & !g & !h) ;
|
201 |
|
|
|
202 |
|
|
assign H = ((j ^ h) & ! ((!f & g & !h & j & !K28p) | (!f & g & h & !j & K28p) |
|
203 |
|
|
(f & !g & !h & j & !K28p) | (f & !g & h & !j & K28p))) | (!f & g & h & j) | (f & !g & !h & !j) ;
|
204 |
|
|
|
205 |
|
|
// ******************************************************************************
|
206 |
|
|
// Registered 8B output
|
207 |
|
|
// ******************************************************************************
|
208 |
|
|
|
209 |
|
|
always @(posedge RBYTECLK or posedge reset)
|
210 |
|
|
if (reset)
|
211 |
|
|
begin
|
212 |
|
|
K_out <= 0; ebi[7:0] <= 8'b0;
|
213 |
|
|
end
|
214 |
|
|
else
|
215 |
|
|
begin
|
216 |
|
|
K_out <= K; ebi[7:0] <= { H, G, F, E, D, C, B, A } ;
|
217 |
|
|
end
|
218 |
|
|
|
219 |
|
|
// ******************************************************************************
|
220 |
|
|
// Disparity
|
221 |
|
|
// ******************************************************************************
|
222 |
|
|
|
223 |
|
|
wire heqj, fghjP13, fghjP31, fghj22;
|
224 |
|
|
|
225 |
|
|
wire DISPARITY6p, DISPARITY6n, DISPARITY4p, DISPARITY4n;
|
226 |
|
|
|
227 |
|
|
wire DISPARITY6b, DISPARITY6a2, DISPARITY6a0;
|
228 |
|
|
|
229 |
|
|
assign feqg = (f & g) | (!f & !g);
|
230 |
|
|
assign heqj = (h & j) | (!h & !j);
|
231 |
|
|
|
232 |
|
|
assign fghjP13 = ( !feqg & !h & !j) | ( !heqj & !f & !g) ;
|
233 |
|
|
assign fghjP31 = ( (!feqg) & h & j) | ( !heqj & f & g) ;
|
234 |
|
|
assign fghj22 = (f & g & !h & !j) | (!f & !g & h & j) | ( !feqg & !heqj) ;
|
235 |
|
|
|
236 |
|
|
assign DISPARITY6p = (P31 & (e | i)) | (P22 & e & i) ;
|
237 |
|
|
assign DISPARITY6n = (P13 & ! (e & i)) | (P22 & !e & !i);
|
238 |
|
|
|
239 |
|
|
assign DISPARITY4p = fghjP31 ;
|
240 |
|
|
assign DISPARITY4n = fghjP13 ;
|
241 |
|
|
|
242 |
|
|
assign DISPARITY6a = P31 | (P22 & disparity); // pos disp if P22 and was pos, or P31.
|
243 |
|
|
assign DISPARITY6a2 = P31 & disparity; // disp is ++ after 4 bts
|
244 |
|
|
assign DISPARITY6a0 = P13 & ! disparity; // -- disp after 4 bts
|
245 |
|
|
|
246 |
|
|
assign DISPARITY6b = (e & i & ! DISPARITY6a0) | (DISPARITY6a & (e | i)) | DISPARITY6a2;
|
247 |
|
|
|
248 |
|
|
|
249 |
|
|
// ******************************************************************************
|
250 |
|
|
// Disparity errors
|
251 |
|
|
// ******************************************************************************
|
252 |
|
|
|
253 |
|
|
wire derr1,derr2,derr3,derr4,derr5,derr6,derr7,derr8;
|
254 |
|
|
|
255 |
|
|
assign derr1 = (disparity & DISPARITY6p) | (DISPARITY6n & !disparity);
|
256 |
|
|
assign derr2 = (disparity & !DISPARITY6n & f & g);
|
257 |
|
|
assign derr3 = (disparity & a & b & c);
|
258 |
|
|
assign derr4 = (disparity & !DISPARITY6n & DISPARITY4p);
|
259 |
|
|
assign derr5 = (!disparity & !DISPARITY6p & !f & !g);
|
260 |
|
|
assign derr6 = (!disparity & !a & !b & !c);
|
261 |
|
|
assign derr7 = (!disparity & !DISPARITY6p & DISPARITY4n);
|
262 |
|
|
assign derr8 = (DISPARITY6p & DISPARITY4p) | (DISPARITY6n & DISPARITY4n);
|
263 |
|
|
|
264 |
|
|
// ******************************************************************************
|
265 |
|
|
// Register disparity and disparity_err output
|
266 |
|
|
// ******************************************************************************
|
267 |
|
|
|
268 |
|
|
reg derr12, derr34, derr56, derr78;
|
269 |
|
|
|
270 |
|
|
always @(posedge RBYTECLK or posedge reset)
|
271 |
|
|
if (reset)
|
272 |
|
|
begin
|
273 |
|
|
disparity <= 1'b0;
|
274 |
|
|
derr12 <= 1;
|
275 |
|
|
derr34 <= 1;
|
276 |
|
|
derr56 <= 1;
|
277 |
|
|
derr78 <= 1;
|
278 |
|
|
end
|
279 |
|
|
else
|
280 |
|
|
begin
|
281 |
|
|
disparity <= fghjP31 | (DISPARITY6b & fghj22) ;
|
282 |
|
|
|
283 |
|
|
derr12 <= derr1 | derr2;
|
284 |
|
|
derr34 <= derr3 | derr4;
|
285 |
|
|
derr56 <= derr5 | derr6;
|
286 |
|
|
derr78 <= derr7 | derr8;
|
287 |
|
|
end
|
288 |
|
|
|
289 |
|
|
assign disparity_err = derr12|derr34|derr56|derr78;
|
290 |
|
|
|
291 |
|
|
// ******************************************************************************
|
292 |
|
|
// Coding errors as defined in patent - page 447
|
293 |
|
|
// ******************************************************************************
|
294 |
|
|
|
295 |
|
|
wire cerr1, cerr2, cerr3, cerr4, cerr5, cerr6, cerr7, cerr8, cerr9;
|
296 |
|
|
|
297 |
|
|
assign cerr1 = (a & b & c & d) | (!a & !b & !c & !d);
|
298 |
|
|
assign cerr2 = (P13 & !e & !i);
|
299 |
|
|
assign cerr3 = (P31 & e & i);
|
300 |
|
|
assign cerr4 = (f & g & h & j) | (!f & !g & !h & !j);
|
301 |
|
|
assign cerr5 = (e & i & f & g & h) | (!e & !i & !f & !g & !h);
|
302 |
|
|
assign cerr6 = (e & !i & g & h & j) | (!e & i & !g & !h & !j);
|
303 |
|
|
assign cerr7 = (((e & i & !g & !h & !j) | (!e & !i & g & h & j)) & !((c & d & e) | (!c & !d & !e)));
|
304 |
|
|
assign cerr8 = (!P31 & e & !i & !g & !h & !j);
|
305 |
|
|
assign cerr9 = (!P13 & !e & i & g & h & j);
|
306 |
|
|
|
307 |
|
|
reg cerr;
|
308 |
|
|
|
309 |
|
|
always @(posedge RBYTECLK or posedge reset)
|
310 |
|
|
if (reset)
|
311 |
|
|
cerr <= 0;
|
312 |
|
|
else
|
313 |
|
|
cerr <= cerr1|cerr2|cerr3|cerr4|cerr5|cerr6|cerr7|cerr8|cerr9;
|
314 |
|
|
|
315 |
|
|
// ******************************************************************************
|
316 |
|
|
// Disparity coding errors curtosy of http://asics.chuckbenz.com/decode.v
|
317 |
|
|
// ******************************************************************************
|
318 |
|
|
|
319 |
|
|
wire zerr1, zerr2, zerr3;
|
320 |
|
|
|
321 |
|
|
assign zerr1 = (DISPARITY6p & DISPARITY4p) | (DISPARITY6n & DISPARITY4n);
|
322 |
|
|
assign zerr2 = (f & g & !h & !j & DISPARITY6p);
|
323 |
|
|
assign zerr3 = (!f & !g & h & j & DISPARITY6n);
|
324 |
|
|
|
325 |
|
|
reg zerr;
|
326 |
|
|
|
327 |
|
|
always @(posedge RBYTECLK or posedge reset)
|
328 |
|
|
if (reset)
|
329 |
|
|
zerr <= 0;
|
330 |
|
|
else
|
331 |
|
|
zerr <= zerr1|zerr2|zerr3;
|
332 |
|
|
|
333 |
|
|
// ******************************************************************************
|
334 |
|
|
// Extra coding errors - again from http://asics.chuckbenz.com/decode.v
|
335 |
|
|
// ******************************************************************************
|
336 |
|
|
|
337 |
|
|
wire xerr1, xerr2, xerr3, xerr4;
|
338 |
|
|
|
339 |
|
|
reg xerr;
|
340 |
|
|
|
341 |
|
|
assign xerr1 = (a & b & c & !e & !i & ((!f & !g) | fghjP13));
|
342 |
|
|
assign xerr2 =(!a & !b & !c & e & i & ((f & g) | fghjP31));
|
343 |
|
|
assign xerr3 = (c & d & e & i & !f & !g & !h);
|
344 |
|
|
assign xerr4 = (!c & !d & !e & !i & f & g & h);
|
345 |
|
|
|
346 |
|
|
always @(posedge RBYTECLK or posedge reset)
|
347 |
|
|
if (reset)
|
348 |
|
|
xerr <= 0;
|
349 |
|
|
else
|
350 |
|
|
xerr <= xerr1|xerr2|xerr3|xerr4;
|
351 |
|
|
|
352 |
|
|
// ******************************************************************************
|
353 |
|
|
// Registered Coding error output
|
354 |
|
|
// ******************************************************************************
|
355 |
|
|
|
356 |
|
|
always @(posedge RBYTECLK or posedge reset)
|
357 |
|
|
if (reset)
|
358 |
|
|
coding_err <= 1'b1;
|
359 |
|
|
else
|
360 |
|
|
coding_err <= cerr | zerr | xerr;
|
361 |
|
|
|
362 |
|
|
endmodule
|