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[/] [1000base-x/] [trunk/] [rtl/] [verilog/] [encoder_8b10b.v] - Blame information for rev 3

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  File name "encoder_8b10b.v"                                 ////
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////                                                              ////
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////  This file is part of the :                                  ////
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////                                                              ////
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//// "1000BASE-X IEEE 802.3-2008 Clause 36 - PCS project"         ////
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////                                                              ////
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////  http://opencores.org/project,1000base-x                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - D.W.Pegler Cambridge Broadband Networks Ltd           ////
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////                                                              ////
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////      { peglerd@gmail.com, dwp@cambridgebroadand.com }        ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 AUTHORS. All rights reserved.             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// This module is based on the coding method described in       ////
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//// IEEE Std 802.3-2008 Section 36.2.4 which is available from : ////
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////                                                              ////
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//// http://standards.ieee.org/about/get/802/802.3.html           ////
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////                                                              ////
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//// and the 8B/10B coding scheme from the 1993 IBM publication   ////
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//// "DC-Balanced, Partitioned-Block, 8B/10B Transmission Code"   ////
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//// by A.X. Widmer and P.A. Franasze" see doc/01-581v1.pdf       ////
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////                                                              ////
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//// and US patent #4,486,739 "BYTE ORIENTED DC BALANCED          ////
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//// (0,4) 8B/10B PARTITIONED BLOCK TRANSMISSION CODE "; see :    ////
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////                                                              ////
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//// doc/US4486739.pdf                                            ////
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////                                                              ////
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//// http://en.wikipedia.org/wiki/8b/10b_encoding                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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module encoder_8b10b (
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   // --- Resets
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   input reset,
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   // --- Clocks
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   input SBYTECLK,
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   // --- Control (K) input       
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   input K,
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   // --- Eight Bt input bus      
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   input [7:0] ebi,
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   // --- TB (Ten Bt Interface) output bus
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   output [9:0] tbi,
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   output reg disparity
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   );
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   // Figure 3 - Encoder: 5B/6B classification, L functions
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   wire   L40, L04, L13, L31, L22, AeqB, CeqD;
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   // Figure 5 - 5B/6B Encoder: disparity classifications
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   wire   PD_1S6, NDOS6, PDOS6, ND_1S6;
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   // Figure 5 - 3B/4B Encoder: disparity classifications
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   wire   ND_1S4, PD_1S4, NDOS4, PDOS4;
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   // Figure 6 - Encoder: control of complementation
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   wire   illegalk, DISPARITY6;
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   reg    COMPLS6, COMPLS4;
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   // Figure 7 - 5B/6B encoding 
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   wire   NAO, NBO, NCO, NDO, NEO, NIO;
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   // Figure 8: 3B/4B encoding
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   wire   NFO, NGO, NHO, NJO;
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   // 8B Inputs
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   wire   A,B,C,D,E,F,G,H;
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   assign {H,G,F,E,D,C,B,A} = ebi[7:0];
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   // 10B Outputs
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   reg    a,b,c,d,e,i,f,g,h,j;
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   assign tbi[9:0] = {a,b,c,d,e,i,f,g,h,j};
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   wire [9:0] tst;
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   assign tst[9:0] = {NAO,NBO,NCO,NDO,NEO,NIO,NFO,NGO,NHO,NJO};
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   // ******************************************************************************
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   // Figures 7 & 8 - Latched 5B/6B and 3B/4B encoder outputs 
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   // ******************************************************************************
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   always @(posedge SBYTECLK, posedge reset)
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     if (reset)
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       begin
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          disparity <= 1'b0; {a,b,c,d,e,i,f,g,h,j} <= 10'b0;
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       end
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     else begin
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        disparity <= (PDOS4 | NDOS4) ^ DISPARITY6;
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        {a,b,c,d,e,i,f,g,h,j} <= { NAO^COMPLS6, NBO^COMPLS6, NCO^COMPLS6,
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                                   NDO^COMPLS6, NEO^COMPLS6, NIO^COMPLS6,
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                                   NFO^COMPLS4, NGO^COMPLS4,
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                                   NHO^COMPLS4, NJO^COMPLS4 };
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     end // else: !if(reset)
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   // ******************************************************************************
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   // Figure 3 - Encoder: 5B/6B classification, L functions
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   // ******************************************************************************
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   assign AeqB = (A & B) | (!A & !B);
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   assign CeqD = (C & D) | (!C & !D);
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   assign L40 =  A & B & C & D ;
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   assign L04 = !A & !B & !C & !D;
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   assign L13 = (!AeqB & !C & !D) | (!CeqD & !A & !B);
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   assign L31 = (!AeqB &  C &  D) | (!CeqD &  A &  B);
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   assign L22 = (A & B & !C & !D) | (C & D & !A & !B) | ( !AeqB & !CeqD) ;
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   // ******************************************************************************
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   // Figure 5 - 5B/6B Encoder: disparity classifications
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   // ******************************************************************************
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   assign PD_1S6 = (E & D & !C & !B & !A) | (!E & !L22 & !L31) ;
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   //assign PD_1S6 = (L13 & D & E) | (!E & !L22 & !L31) ;
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   assign NDOS6  = PD_1S6 ;
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   assign PDOS6  = K | (E & !L22 & !L13) ;
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   assign ND_1S6 = K | (E & !L22 & !L13) | (!E & !D & C & B & A) ;
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   // ******************************************************************************
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   // Figure 5 - 3B/4B Encoder: disparity classifications
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   // ******************************************************************************
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   assign ND_1S4 = F & G ;
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   assign NDOS4  = (!F & !G) ;
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   assign PD_1S4 = (!F & !G) | (K & ((F & !G) | (!F & G)));
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   assign PDOS4  = F & G & H ;
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   // ******************************************************************************
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   // Figure 6 - Encoder: control of complementation
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   // ******************************************************************************
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   // not K28.0->7 & K23/27/29/30.7
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   assign illegalk = K & (A | B | !C | !D | !E) & (!F | !G | !H | !E | !L31);
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   assign DISPARITY6 = disparity ^ (NDOS6 | PDOS6) ;
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   always @(posedge SBYTECLK, posedge reset)
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     if(reset) begin
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       COMPLS4 <= 0;
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       COMPLS6 <= 0;
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       end
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     else begin
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       COMPLS4 <= (PD_1S4 & !DISPARITY6) | (ND_1S4 & DISPARITY6);
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       COMPLS6 <= (PD_1S6 & !disparity) | (ND_1S6 & disparity);
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       end
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   // ******************************************************************************
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   // Figure 7 - 5B/6B encoding 
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   // ******************************************************************************
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   reg tNAO, tNBOx, tNBOy, tNCOx, tNCOy, tNDO , tNEOx, tNEOy, tNIOw, tNIOx, tNIOy, tNIOz;
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   always @(posedge SBYTECLK, posedge reset)
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     if(reset) begin
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       tNAO  <= 0;
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       tNBOx <= 0;
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       tNBOy <= 0;
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       tNCOx <= 0;
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       tNCOy <= 0;
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       tNDO  <= 0;
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       tNEOx <= 0;
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       tNEOy <= 0;
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       tNIOw <= 0;
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       tNIOx <= 0;
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       tNIOy <= 0;
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       tNIOz <= 0;
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       end
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     else begin
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       tNAO  <= A ;
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       tNBOx <= B & !L40;
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       tNBOy <= L04 ;
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       tNCOx <= L04 | C ;
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       tNCOy <= E & D & !C & !B & !A ;
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       tNDO  <= D & ! (A & B & C) ;
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       tNEOx <= E | L13;
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       tNEOy <= !(E & D & !C & !B & !A) ;
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       tNIOw <= (L22 & !E) | (E & L40) ;
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       tNIOx <= E & !D & !C & !(A & B) ;
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       tNIOy <= K & E & D & C & !B & !A ;
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       tNIOz <= E & !D & C & !B & !A ;
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       end
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   assign NAO = tNAO ;
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   assign NBO = tNBOx | tNBOy ;
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   assign NCO = tNCOx | tNCOy ;
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   assign NDO = tNDO ;
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   assign NEO = tNEOx & tNEOy ;
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   assign NIO = tNIOw | tNIOx | tNIOy | tNIOz;
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   // ******************************************************************************
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   // Figure 8: 3B/4B encoding
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   // ******************************************************************************
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   reg alt7, tNFO, tNGO, tNHO, tNJO;
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   always @(posedge SBYTECLK, posedge reset)
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     if(reset) begin
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       alt7 <= 0;
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       tNFO <= 0;
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       tNGO <= 0;
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       tNHO <= 0;
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       tNJO <= 0;
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       end
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     else begin
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       alt7 <= F & G & H & (K | (disparity ? (!E & D & L31) : (E & !D & L13))) ;
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       tNFO <= F;
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       tNGO <= G | (!F & !G & !H) ;
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       tNHO <= H ;
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       tNJO <= !H & (G ^ F) ;
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       end
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   assign NFO = tNFO & !alt7 ;
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   assign NGO = tNGO ;
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   assign NHO = tNHO ;
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   assign NJO = tNJO | alt7 ;
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endmodule
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