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1 3 dwp
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  File name "ge_1000baseX.v"                                  ////
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////                                                              ////
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////  This file is part of the :                                  ////
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////                                                              ////
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//// "1000BASE-X IEEE 802.3-2008 Clause 36 - PCS project"         ////
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////                                                              ////
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////  http://opencores.org/project,1000base-x                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - D.W.Pegler Cambridge Broadband Networks Ltd           ////
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////                                                              ////
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////      { peglerd@gmail.com, dwp@cambridgebroadand.com }        ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 AUTHORS. All rights reserved.             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
////                                                              ////
43
//// This module is based on the coding method described in       ////
44
//// IEEE Std 802.3-2008 Clause 36 "Physical Coding Sublayer(PCS) ////
45
//// and Physical Medium Attachment (PMA) sublayer, type          ////
46
//// 1000BASE-X"; see :                                           ////
47
////                                                              ////
48
//// http://standards.ieee.org/about/get/802/802.3.html           ////
49
//// and                                                          ////
50
//// doc/802.3-2008_section3.pdf, Clause/Section 36.              ////
51
////                                                              ////
52
//////////////////////////////////////////////////////////////////////
53
 
54
`include "timescale.v"
55
 
56
`include "ge_1000baseX_regs.v"
57
`include "ge_1000baseX_constants.v"
58
 
59
 
60
module ge_1000baseX #(
61
  parameter PHY_ADDR = 5'b00000
62
)(
63
   // Clocks 
64
   input             rx_ck,
65
   input             tx_ck,
66
 
67
   // Resets             
68
   input             rx_reset,
69
   input             tx_reset,
70
 
71
   // Startup interface
72
   input             startup_enable,
73
 
74
   // Signal detect from FO transceiver              
75
   input             signal_detect,
76
 
77
   //  RLK1221 receive TBI bus 
78
   input   [9:0]     tbi_rxd,
79
 
80
   //  TLK1221 transmit TBI bus 
81
   output   [9:0]    tbi_txd,
82
 
83
   //  Receive GMII bus 
84
   output      [7:0] gmii_rxd,
85
   output            gmii_rx_dv,
86
   output            gmii_rx_er,
87
   output            gmii_col,
88
   output reg        gmii_cs,
89
 
90
 
91
   //  Transmit GMII bus  
92
   input   [7:0]     gmii_txd,
93
   input             gmii_tx_en,
94
   input             gmii_tx_er,
95
 
96
   input             repeater_mode,
97
 
98
   //  MDIO interface   
99
   input             mdc_reset,
100
   inout             mdio,
101
   input             mdc
102
 
103
  );
104
 
105
   //////////////////////////////////////////////////////////////////////////////
106
   // IEEE Std 802.3-2008 Clause 22 "Reconcilliation Sublayer (RS) and 
107
   // Media Independent Interface (MII)IEEE 802.3-2005 Clause 22 
108
   //////////////////////////////////////////////////////////////////////////////
109
 
110
   wire              mdio_in, mdio_out, mdio_oe;
111
 
112
   wire [15:0]        gmii_reg_wr;
113
   wire [15:0]        gmii_reg_rd;
114
   wire [4:0]         gmii_reg_addr;
115
   wire              gmii_reg_wr_strobe;
116
 
117
   ge_1000baseX_mdio #(
118
    .PHY_ADDR(PHY_ADDR)
119
   ) gmii_mdioi(
120
    .reset(mdc_reset),
121
    .mdc(mdc),
122
    .mdio(mdio_in),
123
    .mdio_out(mdio_out),
124
    .mdio_oe(mdio_oe),
125
 
126
    .data_addr(gmii_reg_addr),
127
    .data_rd(gmii_reg_rd),
128
    .data_wr(gmii_reg_wr),
129
    .strobe_wr(gmii_reg_wr_strobe)
130
   );
131
 
132
   // MDIO tristate drivers.
133
   assign mdio = (mdio_oe) ? mdio_out : 1'bz;
134
 
135
   assign mdio_in = mdio;
136
 
137
   //////////////////////////////////////////////////////////////////////////////
138
   // IEEE 802.3-2008 1000BASE-X PCS OUI and version Number
139
   //////////////////////////////////////////////////////////////////////////////
140
 
141
   wire [23:0]        IEEE_OUI =  24'ha1b2c3;
142
 
143
   wire [7:0]         version = { 4'b0000, 4'b0001 };
144
 
145
   //////////////////////////////////////////////////////////////////////////////
146
   //  Aneg configuration registers
147
   //////////////////////////////////////////////////////////////////////////////
148
 
149
   wire [15:0]    tx_config_reg; wire [15:0] rx_config_reg; wire rx_config_reg_set;
150
 
151
   //////////////////////////////////////////////////////////////////////////////
152
   // GMII  register 0 - Basic Control - IEEE 802.3-8 1000BASE-X clause 37 page 35 
153
   //////////////////////////////////////////////////////////////////////////////
154
 
155
   reg [15:0]     gmii_reg_0;
156
 
157
   wire          mr_main_reset, mr_loopback, mr_restart_an, mr_an_enable;
158
 
159
   assign        mr_main_reset = gmii_reg_0[15];
160
   assign        mr_loopback   = gmii_reg_0[14];
161
   assign        mr_an_enable  = gmii_reg_0[12];
162
   assign        mr_restart_an = gmii_reg_0[9];
163
 
164
`ifdef MODEL_TECH
165
   // Register 0 bit 11 (normally power-down) used in simulation
166
   // to simulate fibre being inserted and removed
167
   //
168
   wire          signal_detect_int = (gmii_reg_0[11] & signal_detect);
169
`else
170
   wire          signal_detect_int = signal_detect;
171
`endif
172
 
173
   //////////////////////////////////////////////////////////////////////////////
174
   // Safe versions of various signals in the RX clock domain
175
   //////////////////////////////////////////////////////////////////////////////
176
 
177
   reg [1:0]      mr_main_reset_rxc, mr_loopback_rxc,  mr_restart_an_rxc;
178
   reg [1:0]      signal_detect_rxc, mr_an_enable_rxc, startup_enable_rxc;
179
 
180
   always @(posedge rx_ck, posedge rx_reset)
181
    if (rx_reset) begin
182
       mr_main_reset_rxc <= 2'b00; mr_loopback_rxc    <= 2'b00;
183
       mr_restart_an_rxc <= 2'b00; mr_an_enable_rxc   <= 2'b00;
184
       signal_detect_rxc <= 2'b00; startup_enable_rxc <= 2'b00;
185
    end
186
    else begin
187
       mr_main_reset_rxc  <= {  mr_main_reset_rxc[0], mr_main_reset     };
188
       mr_loopback_rxc    <= {    mr_loopback_rxc[0], mr_loopback       };
189
       mr_restart_an_rxc  <= {  mr_restart_an_rxc[0], mr_restart_an     };
190
       mr_an_enable_rxc   <= {   mr_an_enable_rxc[0], mr_an_enable      };
191
       signal_detect_rxc  <= {  signal_detect_rxc[0], signal_detect_int };
192
       startup_enable_rxc <= { startup_enable_rxc[0], startup_enable    };
193
    end
194
 
195
   // Speed select - when AN disabled
196
   wire [1:0]         speed_select =  {gmii_reg_0[6], gmii_reg_0[13]};
197
 
198
 
199
`ifdef MODEL_TECH
200
 `define GMII_REG_0_RESET {8'h19, 8'h40}
201
`else
202
 `define GMII_REG_0_RESET {8'h11, h40}
203
`endif
204
 
205
   //////////////////////////////////////////////////////////////////////////////
206
   // GMII register 1 - Basic Status - IEEE 802.3-5 1000baseLX clause 37 page 36 
207
   //////////////////////////////////////////////////////////////////////////////
208
 
209
   wire              mr_an_complete, sync_status;
210
 
211
`ifdef MODEL_TECH
212
   // For simulation - sync_status is on gmii_reg 1 bit 7 - currently unused
213
   wire [15:0]        gmii_reg_1 = { 1'b0,        1'b0,                 1'b0,           1'b0,
214
                                    1'b0,        1'b0,                 1'b0,           1'b0,
215
                                    sync_status, 1'b1,                 mr_an_complete, 1'b0,
216
                                    1'b1,        signal_detect_rxc[1], 1'b0,           1'b0};
217
`else
218
   wire [15:0]        gmii_reg_1 = { 1'b0,        1'b0,                 1'b0,           1'b0,
219
                                    1'b0,        1'b0,                 1'b0,           1'b0,
220
                                    1'b0,        1'b1,                 mr_an_complete, 1'b0,
221
                                    1'b1,        signal_detect_rxc[1], 1'b0,           1'b0};
222
`endif
223
 
224
   //////////////////////////////////////////////////////////////////////////////
225
   // GMII register 2 - PHY Identifier 1 - IEEE 802.3-5 1000baseX 
226
   // clause 37 page 36 
227
   //////////////////////////////////////////////////////////////////////////////
228
 
229
   wire [15:0]        gmii_reg_2 = { IEEE_OUI[15:8], IEEE_OUI[23:16]};
230
 
231
   //////////////////////////////////////////////////////////////////////////////
232
   // --- GMII register 3 - PHY Identifier 2 - IEEE 802.3-5 1000baseX 
233
   // clause 37 page 36
234
   //////////////////////////////////////////////////////////////////////////////
235
 
236
   wire [15:0]        gmii_reg_3 = { version, IEEE_OUI[7:0] };
237
 
238
   //////////////////////////////////////////////////////////////////////////////
239
   // GMII register 4 - Auto-Negotiation Advertisement - IEEE 802.3-5 1000baseX 
240
   // clause 37 page 37 
241
   //////////////////////////////////////////////////////////////////////////////
242
 
243
   reg  [15:0]        gmii_reg_4;
244
 
245
   wire [15:0]        mr_adv_ability;
246
 
247
   // See IEEE 802.3-5 1000baseLX clause 37 page 82 - Table 37-1 for these
248
 
249
   assign            mr_adv_ability = gmii_reg_4;
250
 
251
`define GMII_REG_4_RESET 16'b0000000000100000
252
 
253
   //////////////////////////////////////////////////////////////////////////////
254
   // GMII register 5 - Auto-Negotiation Link Partner Ability - IEEE 802.3-5 
255
   // 1000baseX clause 37 page 37
256
   //////////////////////////////////////////////////////////////////////////////
257
 
258
   wire [15:0]        mr_lp_adv_ability;
259
 
260
   wire [15:0]        gmii_reg_5 = mr_lp_adv_ability;
261
 
262
   //////////////////////////////////////////////////////////////////////////////
263
   // GMII register 6 - Auto-Negotiation Expansion - IEEE 802.3-5 1000baseX 
264
   // clause 37 page 38
265
   //////////////////////////////////////////////////////////////////////////////
266
 
267
   wire [15:0]        gmii_reg_6;
268
 
269
   wire              mr_np_abl, mr_page_rx;
270
 
271
   assign            gmii_reg_6 = { 1'b0,      1'b0, 1'b0,      1'b0,
272
                                    1'b0,      1'b0, 1'b0,      1'b0,
273
                                    1'b0,      1'b0, 1'b0,      1'b0,
274
                                    mr_np_abl, 1'b0, mr_page_rx,1'b0};
275
 
276
   //////////////////////////////////////////////////////////////////////////////
277
   // GMII register 7 - Auto-Negotiation Link Partner Next Page - IEEE 802.3-5 
278
   // 1000baseX clause 37 page 38 
279
   //////////////////////////////////////////////////////////////////////////////
280
 
281
   reg [15:0]         gmii_reg_7;
282
 
283
   wire[15:0]         mr_np_tx;
284
 
285
   assign            mr_np_tx = gmii_reg_7;
286
 
287
`define GMII_REG_7_RESET 16'b0000000000000000
288
 
289
   //////////////////////////////////////////////////////////////////////////////
290
   // GMII register 8 - Auto-Negotiation Link Partner Next Page - IEEE 802.3-5 
291
   // 1000baseX clause 37 page 38
292
   //////////////////////////////////////////////////////////////////////////////
293
 
294
   wire [15:0]        gmii_reg_8;
295
 
296
   wire [15:0]        mr_lp_np_rx;
297
 
298
   assign            gmii_reg_8 = mr_lp_np_rx;
299
 
300
   //////////////////////////////////////////////////////////////////////////////
301
   // IEEE Std 802.3-2008 Clause 22 "Reconcilliation Sublayer (RS) and 
302
   // Media Independent Interface (MII)IEEE 802.3-2005 Clause 22 
303
   //////////////////////////////////////////////////////////////////////////////
304
 
305
   // Read operations
306
   assign gmii_reg_rd = (gmii_reg_addr == `GMII_BASIC_CTRL)       ? gmii_reg_0  :
307
                        (gmii_reg_addr == `GMII_BASIC_STATUS)     ? gmii_reg_1  :
308
                        (gmii_reg_addr == `GMII_PHY_ID1)          ? gmii_reg_2  :
309
                        (gmii_reg_addr == `GMII_PHY_ID2)          ? gmii_reg_3  :
310
                        (gmii_reg_addr == `GMII_AN_ADV)           ? gmii_reg_4  :
311
                        (gmii_reg_addr == `GMII_AN_LP_ADV)        ? gmii_reg_5  :
312
                        (gmii_reg_addr == `GMII_AN_EXPANSION)     ? gmii_reg_6  :
313
                        (gmii_reg_addr == `GMII_AN_NP)            ? gmii_reg_7  :
314
                        (gmii_reg_addr == `GMII_AN_LP_NP)         ? gmii_reg_8  : 5'b00000;
315
 
316
   // Write operations
317
   always @(posedge mdc or posedge mdc_reset)
318
     if (mdc_reset)
319
       begin
320
          gmii_reg_0  <= `GMII_REG_0_RESET;
321
          gmii_reg_4  <= `GMII_REG_4_RESET;
322
          gmii_reg_7  <= `GMII_REG_7_RESET;
323
       end
324
     else
325
       if (gmii_reg_wr_strobe)
326
         begin
327
            case (gmii_reg_addr)
328
 
329
              `GMII_BASIC_CTRL       : gmii_reg_0  <= gmii_reg_wr;
330
              `GMII_AN_ADV           : gmii_reg_4  <= gmii_reg_wr;
331
              `GMII_AN_NP            : gmii_reg_7  <= gmii_reg_wr;
332
            endcase
333
         end
334
       else
335
         begin
336
            // mr_an_restart is self clearing
337
            if (gmii_reg_0[9]) gmii_reg_0[9] <= 1'b0;
338
 
339
            // mr_main_reset) is self clearing
340
            else if (gmii_reg_0[15]) gmii_reg_0[15] <= 1'b0;
341
         end
342
 
343
 
344
   //////////////////////////////////////////////////////////////////////////////
345
   // Status
346
   //////////////////////////////////////////////////////////////////////////////
347
 
348
   wire [2:0]         xmit;
349
 
350
   wire              carrier_detect;
351
 
352
   wire              transmitting, receiving;
353
 
354
   //////////////////////////////////////////////////////////////////////////////
355
   //  Generate GMII Carrier Sense - IEEE 802.3-2008 Clause 36 - 26.2.5.2.5
356
   //////////////////////////////////////////////////////////////////////////////
357
 
358
   always @(posedge rx_ck, posedge rx_reset)
359
     if (rx_reset)
360
       gmii_cs <= 1'b0;
361
     else
362
       if      ((~repeater_mode & transmitting) | receiving)  begin gmii_cs <= 1'b1; end
363
 
364
       else if ((repeater_mode | ~transmitting) & ~receiving) begin gmii_cs <= 1'b0; end
365
 
366
 
367
   //////////////////////////////////////////////////////////////////////////////
368
   // delayed versions of 10b interface 
369
   //////////////////////////////////////////////////////////////////////////////         
370
 
371
   reg [9:0]            tbi_rxd_d1, tbi_rxd_d2, tbi_rxd_d3, tbi_rxd_d4;
372
 
373
   always @(posedge rx_ck, posedge rx_reset)
374
     begin
375
        tbi_rxd_d1 <= (rx_reset) ? 0 : tbi_rxd;
376
        tbi_rxd_d2 <= (rx_reset) ? 0 : tbi_rxd_d1;
377
        tbi_rxd_d3 <= (rx_reset) ? 0 : tbi_rxd_d2;
378
        tbi_rxd_d4 <= (rx_reset) ? 0 : tbi_rxd_d3;
379
     end
380
 
381
   //////////////////////////////////////////////////////////////////////////////
382
   /// 8b10 decoder module
383
   //////////////////////////////////////////////////////////////////////////////
384
 
385
   wire                decoder_K, decoder_disparity_err, decoder_coding_err;
386
 
387
   wire [7:0]           decoder_8b_rxd;
388
 
389
 
390
   decoder_8b10b decoder_8b10bi(
391
 
392
      .RBYTECLK(rx_ck),
393
 
394
      .reset(rx_reset),
395
 
396
      // 10B input
397
      .tbi(tbi_rxd_d1),
398
 
399
      // Data/special code-group ctrl                  
400
      .K_out(decoder_K),
401
 
402
      // 8B output   
403
      .ebi(decoder_8b_rxd),
404
 
405
      // Disparity error 
406
      .disparity_err(decoder_disparity_err),
407
 
408
      // Disparity output  
409
      .disparity(decoder_disparity_out),
410
 
411
      // Coding error 
412
      .coding_err(decoder_coding_err)
413
   );
414
 
415
`ifdef MODEL_TECH
416
   wire [4:0]           decoder_8b_rxd_X;
417
   wire [2:0]           decoder_8b_rxd_Y;
418
 
419
   assign {decoder_8b_rxd_Y, decoder_8b_rxd_X} = decoder_8b_rxd;
420
 
421
`endif
422
 
423
   //////////////////////////////////////////////////////////////////////////////
424
   // Instantiate 802.3-2005 PCS sync module - 802.3-2008 Clause 36
425
   //////////////////////////////////////////////////////////////////////////////  
426
 
427
   wire                sync_K, sync_rx_even;
428
   wire [7:0]           sync_8b_rxd;
429
 
430
`ifdef MODEL_TECH
431
   wire [4:0]           sync_8b_rxd_X = sync_8b_rxd[4:0];
432
   wire [2:0]           sync_8b_rxd_Y = sync_8b_rxd[7:5];
433
`endif
434
 
435
   ge_1000baseX_sync ge_1000baseX_sync_i(
436
 
437
      .ck(rx_ck), .reset(rx_reset),
438
 
439
      .startup_enable(startup_enable_rxc[1]),
440
 
441
      // Signal detect from FO transceiver           
442
      .signal_detect(signal_detect_rxc[1]),
443
 
444
      // 8B input from 8b10 decoder 
445
      .ebi_rxd(decoder_8b_rxd),
446
      .ebi_K(decoder_K),
447
 
448
      // 8B output from sync
449
      .ebi_rxd_out(sync_8b_rxd),
450
      .ebi_K_out(sync_K),
451
 
452
       // Synchronisation status
453
      .sync_status(sync_status),
454
 
455
      .rx_even(sync_rx_even),
456
 
457
      .decoder_disparity_err(decoder_disparity_err),
458
 
459
      .decoder_coding_err(decoder_coding_err),
460
 
461
      .loopback(mr_loopback_rxc[1])
462
   );
463
 
464
   //////////////////////////////////////////////////////////////////////////////
465
   // Carrier Detect - IEEE 802.3-2008 Section 36.2.5.1.4
466
   //////////////////////////////////////////////////////////////////////////////
467
 
468
   wire [5:0]           sb; wire [3:0] fb;
469
 
470
   wire                RDn_cd_fail_match1, RDn_cd_fail_match2, RDn_cd_fail_match;
471
 
472
   wire                RDp_cd_fail_match1, RDp_cd_fail_match2,  RDp_cd_fail_match;
473
 
474
   assign              sb[5:0] = tbi_rxd_d4[9:4];
475
 
476
   assign              fb[3:0] = tbi_rxd_d4[3:0];
477
 
478
   assign              RDn_cd_fail_match1 = ((sb == 6'b110000) & ((fb == 4'b0101) | (fb == 4'b0100) | (fb == 4'b0111) | (fb == 4'b0001) | (fb==4'b1101)));
479
 
480
   assign              RDn_cd_fail_match2 = ((fb == 4'b0101) & ((sb==6'b110001) |(sb==6'b110010) | (sb==6'b110100) | (sb==6'b111000) | (sb==6'b100000) | (sb==6'b010000)));
481
 
482
   assign              RDn_cd_fail_match = RDn_cd_fail_match1 | RDn_cd_fail_match2;
483
 
484
 
485
   assign              RDp_cd_fail_match1 = ((sb == 6'b001111) & ((fb==4'b1010)|(fb==4'b1011)|(fb==4'b1000)|(fb==4'b1110)|(fb==4'b0010)));
486
 
487
   assign              RDp_cd_fail_match2 = ((fb == 4'b1010) & ((sb==6'b001110)|(sb==6'b001101)|(sb==6'b001011)|(sb==6'b000111)|(sb==6'b011111)|(sb==6'b101111)));
488
 
489
   assign              RDp_cd_fail_match = RDp_cd_fail_match1 | RDp_cd_fail_match2;
490
 
491
   assign              carrier_detect = sync_rx_even &  ~RDn_cd_fail_match & ~RDp_cd_fail_match;
492
 
493
   //////////////////////////////////////////////////////////////////////////////
494
   // 802.3-2008 1000baseX PCS autonegotiation (AN) module - 802.3-2008 Clause 37
495
   //////////////////////////////////////////////////////////////////////////////
496
 
497
   wire [2:0]           rudi; // RX_UNITDATA.indicate messages
498
 
499
   ge_1000baseX_an ge_1000baseX_an_i(
500
 
501
       .ck(rx_ck),.reset(rx_reset),
502
 
503
       .startup_enable(startup_enable_rxc[1]),
504
 
505
       //  Auto-negotiation ctrl 
506
       .xmit(xmit),
507
       .rx_config(rx_config_reg),
508
       .rx_config_set(rx_config_reg_set),
509
       .tx_config(tx_config_reg),
510
 
511
       // RX_UNITDATA.indicate messages                
512
       .rudi(rudi),
513
 
514
       // Auto-negotiation /C/ and /I/ matching                        
515
       .ability_match(ability_match),
516
       .acknowledge_match(acknowledge_match),
517
       .consistency_match(consistency_match),
518
       .idle_match(idle_match),
519
 
520
       // Synchronisation Status 
521
       .sync_status(sync_status),
522
       .signal_detect(signal_detect_rxc[1]),
523
 
524
       // GMII Register 0 - AN Basic Control
525
       .mr_main_reset(mr_main_reset_rxc[1]),
526
       .mr_loopback(mr_loopback_rxc[1]),
527
       .mr_restart_an(mr_restart_an_rxc[1]),
528
       .mr_an_enable(mr_an_enable_rxc[1]),
529
 
530
       // GMII Register 1 - AN Basic Status                  
531
       .mr_an_complete(mr_an_complete),
532
 
533
       // GMII register 4 - AN Advertisement         
534
       .mr_adv_ability(mr_adv_ability),
535
 
536
       // GMII register 5 - AN Link Partner Ability
537
       .mr_lp_adv_ability(mr_lp_adv_ability),
538
 
539
       // GMII register 6 - AN Expansion
540
       .mr_np_abl(mr_np_abl),
541
       .mr_page_rx(mr_page_rx),
542
 
543
       // GMII register 7 - AN Next Page
544
       .mr_np_tx(mr_np_tx),
545
 
546
       // GMII register 8 - AN Link Partner Next Page   
547
       .mr_lp_np_rx(mr_lp_np_rx)
548
   );
549
 
550
   wire                tx_frame_pulse, frame_rx_pulse;
551
 
552
   //////////////////////////////////////////////////////////////////////////////
553
   // 802.3-2008 1000baseX PCS receive module - 802.3-2008 Clause 36
554
   //////////////////////////////////////////////////////////////////////////////
555
 
556
   ge_1000baseX_rx ge_1000base_rxi(
557
 
558
      .ck(rx_ck), .reset(rx_reset),
559
 
560
      // Receive 8B bus from sync module 
561
      .ebi_rxd(sync_8b_rxd),
562
      .ebi_K(sync_K),
563
 
564
      .rx_even(sync_rx_even),
565
      .carrier_detect(carrier_detect),
566
      .sync_status(sync_status),
567
 
568
      // Signal detect from FO transceiver           
569
      .signal_detect(signal_detect_rxc[1]),
570
 
571
       // Receive frame pulse   
572
      .rx_frame_pulse(rx_frame_pulse),
573
 
574
       // Receive GMII bus 
575
      .gmii_rxd(gmii_rxd),
576
      .gmii_rx_dv(gmii_rx_dv),
577
      .gmii_rx_er(gmii_rx_er),
578
 
579
       // Auto-negotiation ctrl 
580
       .xmit(xmit),
581
       .mr_main_reset(mr_main_reset_rxc[1]),
582
       .rx_config(rx_config_reg),
583
       .rx_config_set(rx_config_reg_set),
584
       .rudi(rudi),
585
 
586
       // Auto-negotiation /C/ and /I/ matching                       
587
       .ability_match(ability_match),
588
       .acknowledge_match(acknowledge_match),
589
       .consistency_match(consistency_match),
590
       .idle_match(idle_match),
591
 
592
       .receiving(receiving)
593
   );
594
 
595
   //////////////////////////////////////////////////////////////////////////////
596
   //  Safe versions of various signals in the TX clock domain
597
   //////////////////////////////////////////////////////////////////////////////
598
 
599
   reg [1:0] mr_main_reset_txc, receiving_txc, signal_detect_txc, startup_enable_txc;
600
 
601
   always @(posedge tx_ck, posedge tx_reset)
602
     if (tx_reset) begin
603
 
604
        mr_main_reset_txc <= 2'b00; receiving_txc      <= 2'b00;
605
        signal_detect_txc <= 2'b00; startup_enable_txc <= 2'b00;
606
     end
607
     else
608
       begin
609
          mr_main_reset_txc  <= {  mr_main_reset_txc[0], mr_main_reset  };
610
          receiving_txc      <= {      receiving_txc[0], receiving      };
611
          signal_detect_txc  <= {  signal_detect_txc[0], signal_detect  };
612
          startup_enable_txc <= { startup_enable_txc[0], startup_enable };
613
       end
614
 
615
   reg [2:0] xmit_txc, xmit_txc0;
616
 
617
   always @(posedge tx_ck, posedge tx_reset)
618
     begin
619
        xmit_txc <= (tx_reset) ? `XMIT_IDLE :  xmit_txc0;
620
 
621
        xmit_txc0 <= (tx_reset) ? `XMIT_IDLE : xmit;
622
     end
623
 
624
   //////////////////////////////////////////////////////////////////////////////
625
   // 802.3-2008 1000baseX PCS transmit module  802.3-2008 Clause 36
626
   //////////////////////////////////////////////////////////////////////////////
627
 
628
   ge_1000baseX_tx ge_1000baseX_txi(
629
 
630
      // --- TX clock and reset ---           
631
      .ck(tx_ck),
632
      .reset(tx_reset),
633
 
634
       // --- RLK1221 transmit TBI bus ---                     
635
      .tbi_txd(tbi_txd),
636
 
637
      .signal_detect(signal_detect_txc[1]),
638
 
639
       // Transmit frame pulse  
640
      .tx_frame_pulse(tx_frame_pulse),
641
 
642
       // --- Transmit GMII bus - 
643
      .gmii_tx_en_in(gmii_tx_en),
644
      .gmii_tx_er_in(gmii_tx_er),
645
      .gmii_txd_in(gmii_txd),
646
 
647
      .gmii_col(gmii_col),
648
 
649
      .receiving(receiving_txc[1]),
650
      .transmitting(transmitting),
651
 
652
       // --- Auto-negotiation ctrl ---
653
      .xmit(xmit_txc),
654
      .tx_config(tx_config_reg),
655
      .mr_main_reset(mr_main_reset_txc[1])
656
   );
657
 
658
   //////////////////////////////////////////////////////////////////////////////
659
   // Frame transmit LED pulse
660
   //////////////////////////////////////////////////////////////////////////////
661
 
662
   reg [23:0]           tx_led_counter;
663
   reg                 tx_frame_pulse_latch, tx_frame_activity;
664
 
665
   always @(posedge tx_ck, posedge tx_reset)
666
 
667
     if (tx_reset)
668
       begin
669
          tx_led_counter <= 0; tx_frame_activity <= 0;  tx_frame_pulse_latch <= 1;
670
       end
671
     else
672
       begin
673
          tx_led_counter <= tx_led_counter + 1;
674
 
675
          if (tx_frame_activity)
676
            begin
677
               if (~tx_led_counter[23]) begin tx_frame_pulse_latch <= 0;tx_frame_activity <= 0; end
678
            end
679
          else if (tx_led_counter[23] & tx_frame_pulse_latch) tx_frame_activity <= 1;
680
 
681
          else if (tx_frame_pulse) tx_frame_pulse_latch <= 1;
682
       end
683
 
684
   //////////////////////////////////////////////////////////////////////////////
685
   // Frame receive LED pulse
686
   //////////////////////////////////////////////////////////////////////////////
687
 
688
   reg [23:0]           rx_led_counter;
689
   reg                 rx_frame_pulse_latch, rx_frame_activity;
690
 
691
   always @(posedge rx_ck, posedge rx_reset)
692
 
693
     if (rx_reset)
694
       begin
695
          rx_led_counter <= 0; rx_frame_activity <= 0;  rx_frame_pulse_latch <= 1;
696
       end
697
     else
698
       begin
699
          rx_led_counter <= rx_led_counter + 1;
700
 
701
          if (rx_frame_activity)
702
            begin
703
               if (~rx_led_counter[23]) begin rx_frame_pulse_latch <= 0;rx_frame_activity <= 0; end
704
            end
705
          else if (rx_led_counter[23] & rx_frame_pulse_latch) rx_frame_activity <= 1;
706
 
707
          else if (rx_frame_pulse) rx_frame_pulse_latch <= 1;
708
       end
709
 
710
 
711
   wire fo_activity = rx_frame_activity | tx_frame_activity;
712
 
713
endmodule

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