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[/] [1000base-x/] [trunk/] [testbench/] [rtl/] [verilog/] [encoder_10b_rx_model.v] - Blame information for rev 4

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1 4 dwp
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  File name "encoder_10b_rx_model.v"                          ////
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////                                                              ////
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////  This file is part of the :                                  ////
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////                                                              ////
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//// "1000BASE-X IEEE 802.3-2008 Clause 36 - PCS project"         ////
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////                                                              ////
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////  http://opencores.org/project,1000base-x                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - D.W.Pegler Cambridge Broadband Networks Ltd           ////
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////                                                              ////
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////      { peglerd@gmail.com, dwp@cambridgebroadand.com }        ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 AUTHORS. All rights reserved.             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// This module is based on the coding method described in       ////
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//// IEEE Std 802.3-2008 Clause 36 "Physical Coding Sublayer(PCS) ////
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//// and Physical Medium Attachment (PMA) sublayer, type          ////
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//// 1000BASE-X"; see :                                           ////
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////                                                              ////
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//// http://standards.ieee.org/about/get/802/802.3.html           ////
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//// and                                                          ////
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//// doc/802.3-2008_section3.pdf, Clause/Section 36.              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`include "timescale_tb.v"
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module encoder_10b_rx_model #(
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  parameter DEBUG       = 0,
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  parameter out_delay   = 5,
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  parameter in_delay    = 2
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)(
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  interface check_intf,
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   // --- Clocks
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   input SBYTECLK,
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   input reset,
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   // --- Ten bit input bus       
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   input [9:0] tbi_rx
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);
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   //----------------------------------------------------------------------------
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  // Checker interface functions
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  //----------------------------------------------------------------------------
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   function automatic string check_intf.whoami();
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      string buffer;
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      $sformat(buffer, "%m");
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      return buffer.substr(0, buffer.len()-17);
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   endfunction
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   //----------------------------------------------------------------------------
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   // 10B symbol, disparity and coding checker 
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   //----------------------------------------------------------------------------
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   integer     iteration = 0;
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   reg [9:0]   checker_10b_symbol = 10'b0; reg [7:0] checker_8B_symbol = 8'b0;
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   reg         null_rd, checker_rd, checker_k, checker_rd_err, checker_code_err;
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   integer     checker_x, checker_y, checker_errors;
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   task automatic encoder_10b_checker();
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      // Pull the next byte
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      checker_10b_symbol = tbi_rx;
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      // Decode the 10b symbol from the checker model
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      encoder_8b10b_threads::decode(checker_10b_symbol, checker_rd, checker_rd, checker_k,
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                                    checker_8B_symbol, checker_rd_err, checker_code_err);
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      // Split the 8b symbol into 5b/6b and 3b/4b components x and y - Dx.y and Kx.y 
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      encoder_8b10b_threads::split(checker_8B_symbol, checker_x, checker_y);
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      // Only check for errors after the first symbol
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      //if (DEBUG | (iteration & (checker_rd_err | checker_code_err)))
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      if (DEBUG)
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        begin
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           $display("Checker 10b %08d: [10b_symbol = %010b, RD = %01b, 8B_symbol = %08b, K = %01b, RD_err = %01b, CODE_err = %01b] : %s : %s%02d.%01d",
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                    iteration, checker_10b_symbol,
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                    checker_rd,  checker_8B_symbol, checker_k,
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                    checker_rd_err, checker_code_err,
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                    ((checker_rd_err | checker_code_err) ? "FAIL" : "PASSED"),
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                    ((checker_k) ? "K" : "D"), checker_x, checker_y);
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           // Halt if disparity or coding errors
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           if (!DEBUG) $stop;
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        end
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      iteration++;
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   endtask // automatic
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  initial
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    begin
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       // Intlialise disparity and coding errors
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       checker_k = 0; checker_rd_err = 0; checker_code_err = 0;
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       // Initialise checker 8B/10b generation
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       encoder_8b10b_threads::init(null_rd, checker_rd, checker_errors);
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       // On startup, the receiver (decoder) should assume +ve or -ve disparity
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       // See IEEE 802.3-2005 Clause 35 - 36.2.4.4
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       // I'm overiding the statup disparity set in encoder_8b10b_threads::init
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       // so that it starts as -ve.
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       checker_rd = 0;
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       // Obtain initial sync...
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       @(posedge SBYTECLK);
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       while (~reset)
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         begin
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            // Handle receive from TBI interface
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            encoder_10b_checker();
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            @(posedge SBYTECLK);
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         end
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    end
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endmodule
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