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[/] [1000base-x/] [trunk/] [testbench/] [rtl/] [verilog/] [ge_1000baseX_tb.v] - Blame information for rev 4

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1 4 dwp
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  File name "ge_1000baseX_tb.v"                               ////
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////                                                              ////
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////  This file is part of the :                                  ////
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////                                                              ////
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//// "1000BASE-X IEEE 802.3-2008 Clause 36 - PCS project"         ////
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////                                                              ////
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////  http://opencores.org/project,1000base-x                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - D.W.Pegler Cambridge Broadband Networks Ltd           ////
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////                                                              ////
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////      { peglerd@gmail.com, dwp@cambridgebroadand.com }        ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 AUTHORS. All rights reserved.             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// This module is based on the coding method described in       ////
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//// IEEE Std 802.3-2008 Clause 36 "Physical Coding Sublayer(PCS) ////
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//// and Physical Medium Attachment (PMA) sublayer, type          ////
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//// 1000BASE-X"; see :                                           ////
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////                                                              ////
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//// http://standards.ieee.org/about/get/802/802.3.html           ////
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//// and                                                          ////
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//// doc/802.3-2008_section3.pdf, Clause/Section 36.              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`include "timescale_tb.v"
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module ge_1000baseX_tb #(
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  parameter test_name = "",
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  parameter quit_on_stop = 0
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) ();
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   //////////////////////////////////////////////////////////////////////
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   // Clock and reset generation.
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   //////////////////////////////////////////////////////////////////////
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   localparam mdio_ck_period            = 1000ns;
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   localparam GE_125MHz_ref_ck_period   = 8ns;
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   reg       running;
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   // Generate MDIO clock (MDC)
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   clock_gen #(.period(mdio_ck_period)) mdio_ck_gen(.enable(running), .ck(mdc));
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   // Generate 125MHz clock reference.
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   clock_gen #(.period( GE_125MHz_ref_ck_period)) GE_125MHz_ref_ck_gen(.enable(running), .ck(GE_125MHz_ref_ckpin));
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   ///////////////////////////////////////////////////////////////////////////////////////////////////
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   // De-assert main reset 10 clocks after startup
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   ///////////////////////////////////////////////////////////////////////////////////////////////////
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   reg       reset;
82
 
83
   initial
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   begin
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      reset = 1;
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      repeat(50) @(posedge GE_125MHz_ref_ckpin);
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      reset = 0;
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    end
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  ///////////////////////////////////////////////////////////////////////////////////////////////////
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  // Handle to all the virtual interfaces of the testbench models.
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  ///////////////////////////////////////////////////////////////////////////////////////////////////
93
 
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   tb_utils::VirIntfHandle h = new();
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   ///////////////////////////////////////////////////////////////////////////////////////////////////
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   // 8B10B bus and PCS GMII interfaces
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   ///////////////////////////////////////////////////////////////////////////////////////////////////
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   wire [9:0] tbi_rxd, tbi_txd;
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   ///////////////////////////////////////////////////////////////////////////////////////////////////
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   // PCS GMII interfaces
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   ///////////////////////////////////////////////////////////////////////////////////////////////////
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   wire [7:0] gmii_rxd, gmii_txd;
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   wire       gmii_rx_dv, gmii_rx_er, gmii_col, gmii_cs, gmii_tx_en, gmii_tx_er;
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   ///////////////////////////////////////////////////////////////////////////////////////////////////
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   // Assert signal_detect a number of clocks after startup
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   ///////////////////////////////////////////////////////////////////////////////////////////////////
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   wire       sync = 1'b1; reg        signal_detect;
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   initial
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     begin
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        signal_detect = 1'b0;
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        repeat(1000) @(posedge GE_125MHz_ref_ckpin);
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        signal_detect = 1'b1;
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     end
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   ///////////////////////////////////////////////////////////////////////////////////////////////////
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   // Loopback on 10B TX and RX interface
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   ///////////////////////////////////////////////////////////////////////////////////////////////////
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   assign tbi_rxd = tbi_txd;
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   ///////////////////////////////////////////////////////////////////////////////////////////////////
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   //  
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   ///////////////////////////////////////////////////////////////////////////////////////////////////
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   wire       sync_en, loop_en, prbs_en;
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   ge_1000baseX_test ge_1000baseX_testi(
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      // --- Resets ---                          
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      .reset_pin(reset),
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      // --- 125MHz Ref clk                              
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      .GE_125MHz_ref_ckpin(GE_125MHz_ref_ckpin),
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      // --- FO TBI 125MHz Rx clk                        
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      .tbi_rx_ckpin(GE_125MHz_ref_ckpin),
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      // --- TLK1221 transmit TBI bus ---                    
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      .tbi_txd(tbi_txd),
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      .tbi_rxd(tbi_rxd),
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      // --- Receive GMII bus --- 
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      .gmii_rxd(gmii_rxd),
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      .gmii_rx_dv(gmii_rx_dv),
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      .gmii_rx_er(gmii_rx_er),
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      .gmii_col(gmii_col),
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      .gmii_cs(gmii_cs),
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       // --- Transmit GMII bus ---                  
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      .gmii_tx_en(gmii_tx_en),
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      .gmii_tx_er(gmii_tx_er),
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      .gmii_txd(gmii_txd),
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      // --- Ctrl/status strobes --- 
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      .sync_en(sync_en),
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      .loop_en(loop_en),
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      .prbs_en(prbs_en),
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      .signal_detect(signal_detect),
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      .sync(sync),
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      // --- MDIO interface ---       
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      .mdio(mdio),
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      .mdio_ckpin(mdc)
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   );
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   ///////////////////////////////////////////////////////////////////////////////////////////////////
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   // GMII bus tx model
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   ///////////////////////////////////////////////////////////////////////////////////////////////////
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   gmii_tx_if gmii_tx_model_if_i();
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   gmii_tx_model #(
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    .DEBUG(1)
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  ) phy_gmii_tx_model_i (
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    .send_intf(gmii_tx_model_if_i.model),
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    .mii_txck_in(1'b0),
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    .gmii_txck_in(GE_125MHz_ref_ckpin),
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    .txck_out(),
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    .gigabit_mode(),
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    .txd(gmii_txd),
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    .tx_en(gmii_tx_en),
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    .tx_er(gmii_tx_er),
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    .crs(gmii_cs),
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    .col(gmii_col)
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  );
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  initial h.gmii_tx_model = gmii_tx_model_if_i;
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  ///////////////////////////////////////////////////////////////////////////////////////////////////
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  // GMII bus rx model
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  ///////////////////////////////////////////////////////////////////////////////////////////////////
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  gmii_rx_if gmii_rx_model_if_i();
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  gmii_rx_model #(
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    .DEBUG(2)
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  ) gmii_rx_model_i(
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    .check_intf(gmii_rx_model_if_i.model),
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    .mii_rxck_in(1'b0),
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    .gmii_rxck_in(GE_125MHz_ref_ckpin),
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    .mii_rxck_out(),
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    .rxd(gmii_rxd),
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    .rx_dv(gmii_rx_dv),
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    .rx_er(gmii_rx_er)
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  );
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   initial h.gmii_rx_model = gmii_rx_model_if_i;
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   ///////////////////////////////////////////////////////////////////////////////////////////////////
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   // mdio mdc serial interface model
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   ///////////////////////////////////////////////////////////////////////////////////////////////////
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   serial_model_if serial_model_if_i();
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   mdio_serial_model #(
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    .PHY_ADDR(5'b00000)
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  ) mdio_serial_model_i (
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    .cmd_intf(serial_model_if_i.model),
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    .reset(reset),
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    .mdc(mdc),
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    .mdio(mdio)
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  );
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   initial h.serial_model = serial_model_if_i;
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   ///////////////////////////////////////////////////////////////////////////////////////////////////
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   // 8B10B 10B receive model
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   ///////////////////////////////////////////////////////////////////////////////////////////////////
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   encoder_10b_rx_if encoder_10b_rx_model_ifi();
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   encoder_10b_rx_model #(
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     .DEBUG(1)
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   ) encoder_10b_rx_modeli (
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     .check_intf(encoder_10b_rx_model_ifi.model),
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     .reset(reset),
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     .SBYTECLK(GE_125MHz_ref_ckpin),
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258
     .tbi_rx(tbi_rxd)
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  );
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   initial h.encoder_10b_rx_model = encoder_10b_rx_model_ifi;
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   ///////////////////////////////////////////////////////////////////////////////////////////////////
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  // Test script selection and launch.
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  ///////////////////////////////////////////////////////////////////////////////////////////////////
266
  int errors;
267
 
268
  initial
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    begin
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      errors = 0; running = 1;
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272
      #0;
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274
      case(test_name)
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        "ge_1000baseX_tb": ge_1000baseX_tb_script::main(h, errors);
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        default:
277
          begin
278
            errors++;
279
            $display("%m:Unknown test '%s'", test_name);
280
          end
281
      endcase
282
 
283
      running = 0;
284
 
285
       $display("Test completed,",);
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287
       if(errors)  $display("%0d errors", errors);
288
       else        $display("success.");
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290
       if (quit_on_stop) $finish;
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       else
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         $stop;
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    end
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endmodule

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