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[/] [1000base-x/] [trunk/] [testbench/] [rtl/] [verilog/] [ge_1000baseX_utils.v] - Blame information for rev 4

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1 4 dwp
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  File name "ge_1000baseX_utils.v"                            ////
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////                                                              ////
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////  This file is part of the :                                  ////
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////                                                              ////
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//// "1000BASE-X IEEE 802.3-2008 Clause 36 - PCS project"         ////
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////                                                              ////
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////  http://opencores.org/project,1000base-x                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - D.W.Pegler Cambridge Broadband Networks Ltd           ////
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////                                                              ////
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////      { peglerd@gmail.com, dwp@cambridgebroadand.com }        ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 AUTHORS. All rights reserved.             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`include "timescale_tb.v"
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`include "ge_1000baseX_regs.v"
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package ge_1000baseX_utils;
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   import tb_utils::VirIntfHandle;
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   task automatic reg_write(VirIntfHandle vih, int addr, reg [15:0] data);
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      vih.serial_model.write(addr, data);
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   endtask
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   task automatic reg_read(VirIntfHandle vih, int addr, output reg [15:0] val);
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      vih.serial_model.read(addr, val);
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   endtask
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   task automatic signal_detect_ctrl(VirIntfHandle vih, int s);
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      reg [15:0] b;
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      reg_read(vih,`GMII_BASIC_CTRL, b);
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      if (s==0) begin b &= ~(16'h0800); end else begin b |= 16'h0800; end
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      reg_write(vih, `GMII_BASIC_CTRL, (b & 16'hffff));
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   endtask
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   task automatic unplug_fo(VirIntfHandle vih);
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      $display("%m: FO interface unplugged", );
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      signal_detect_ctrl(vih, 0);
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   endtask // automatic
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    task automatic insert_fo(VirIntfHandle vih);
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       $display("%m: FO interface inserted");
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       signal_detect_ctrl(vih, 1);
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    endtask // automatic
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   task automatic read_phy_ident(VirIntfHandle vih);
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      reg [15:0] id1,  id2;
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      reg_read(vih,`GMII_PHY_ID1, id1); reg_read(vih,`GMII_PHY_ID2, id2);
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      $display("%m: 1000baseX PCS OUI: %02h%02h%02h - ver %02d.%02d",
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               id1[7:0], id1[15:8], id2[7:0], id2[15:12], id2[11:8]);
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   endtask
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   task automatic reset_aneg(VirIntfHandle vih);
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      reg [15:0] basic_ctrl;
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      $display("%m");
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      reg_read(vih,`GMII_BASIC_CTRL, basic_ctrl);
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      basic_ctrl = (basic_ctrl & 16'hffff) | 16'h8000;
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      reg_write(vih, `GMII_BASIC_CTRL, basic_ctrl);
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   endtask // automatic
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   task automatic restart_aneg(VirIntfHandle vih);
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      reg [15:0] basic_ctrl;
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      $display("%m");
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      reg_read(vih,`GMII_BASIC_CTRL, basic_ctrl);
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      basic_ctrl = (basic_ctrl & 16'hffff) | 16'h0200;
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      reg_write(vih, `GMII_BASIC_CTRL, basic_ctrl);
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   endtask // automatic
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   task automatic signal_detect_poll(VirIntfHandle vih);
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      reg [15:0] status =  0; reg [31:0] counter = 0;
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      $display("%m");
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      while(!status[2])
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        begin
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           reg_read(vih, `GMII_BASIC_STATUS, status);
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           $display("%m: %u: Waiting for signal_detect - status is %16b", counter, status);
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           counter +=1;
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        end
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   endtask
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   task automatic aneg_complete_poll(VirIntfHandle vih);
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      reg [31:0] cnt = 0; reg [15:0] basic_status =  0;
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      $display("%m");
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      while(!basic_status[5])
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        begin
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           reg_read(vih, `GMII_BASIC_STATUS, basic_status);  cnt +=1;
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           $display("%m: Polling ANEG complete : %16b : attempt %d", basic_status, cnt);
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        end
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   endtask
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     task automatic read_aneg_link_partner_capablities(VirIntfHandle vih);
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      reg [15:0] lp_adv;
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      reg_read(vih,`GMII_AN_LP_ADV, lp_adv);
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      $display("%m: ANEG Link Partner capability: %04h", lp_adv);
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   endtask
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endpackage
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