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[/] [1000base-x/] [trunk/] [testbench/] [rtl/] [verilog/] [interfaces.v] - Blame information for rev 4

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1 4 dwp
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  File name "interfaces.v"                                    ////
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////                                                              ////
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////  This file is part of the :                                  ////
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////                                                              ////
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//// "1000BASE-X IEEE 802.3-2008 Clause 36 - PCS project"         ////
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////                                                              ////
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////  http://opencores.org/project,1000base-x                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - D.W.Pegler Cambridge Broadband Networks Ltd           ////
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////                                                              ////
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////      { peglerd@gmail.com, dwp@cambridgebroadand.com }        ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 AUTHORS. All rights reserved.             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`include "timescale_tb.v"
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import ethernet_frame::EthernetFrame;
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import ethernet_frame::FrameMailBox;
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import ethernet_frame::ethernet_address_t;
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import ethernet_frame::EthernetSpeed;
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interface serial_model_if();
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  modport testbench(
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    import function string whoami(),
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    import task write(int address, integer value),
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    import task read(int address, output integer value)
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  );
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  modport model(
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    export function string whoami(),
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    export task write(),
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    export task read()
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  );
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endinterface
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interface gmii_tx_if();
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  modport testbench(
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    import function string whoami(),
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    import function void queue_frame(EthernetFrame frame),
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    import function void queue_delay(time delay),
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    import task sleep(time timeout),
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    import function void set_speed(EthernetSpeed m)
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  );
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  modport model(
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    export function string whoami(),
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    export function void queue_frame(),
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    export function void queue_delay(),
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    export task sleep(),
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    export function void set_speed()
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  );
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endinterface
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interface gmii_rx_if();
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  modport testbench(
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    import function string whoami(),
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    import function void register_mailbox(ethernet_address_t sa, FrameMailBox mbx),
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    import function void unregister_mailbox(ethernet_address_t sa),
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    import function void enable_loopback(virtual gmii_tx_if intf),
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    import function void set_parity_errors(int parity, int errors),
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    import function void set_speed(EthernetSpeed m)
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  );
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  modport model(
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    export function string whoami(),
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    export function void register_mailbox(),
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    export function void unregister_mailbox(),
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    export function void enable_loopback(virtual gmii_tx_if intf),
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    export function void set_parity_errors(),
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    export function void set_speed()
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  );
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endinterface
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interface encoder_8b_tx_if();
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  modport testbench(
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    import function string whoami(),
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    import function void push_8B_symbol(reg[7:0] value),
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    import function void push_config(reg[15:0] value),
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    import function void queue_frame(EthernetFrame frame),
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    import task sleep(time timeout)
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  );
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  modport model(
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    export function string whoami(),
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    export function void push_8B_symbol(),
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    export function void push_config(),
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    export function void queue_frame(),
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    export task sleep()
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  );
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endinterface
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interface encoder_10b_rx_if();
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  modport testbench(
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    import function string whoami()
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  );
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  modport model(
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    export function string whoami()
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  );
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endinterface
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interface decoder_8b_rx_if();
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  modport testbench(
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    import function string whoami()
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  );
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  modport model(
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    export function string whoami()
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  );
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endinterface
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