OpenCores
URL https://opencores.org/ocsvn/10_100m_ethernet-fifo_convertor/10_100m_ethernet-fifo_convertor/trunk

Subversion Repositories 10_100m_ethernet-fifo_convertor

[/] [10_100m_ethernet-fifo_convertor/] [verilog/] [Ethernet.fit.summary] - Blame information for rev 10

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 10 antiquity
Fitter Status : Successful - Sun Dec 13 21:49:10 2009
2
Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version
3
Revision Name : Ethernet
4
Top-level Entity Name : test_feedback
5
Family : Cyclone III
6
Device : EP3C40Q240C8
7
Timing Models : Final
8
Total logic elements : 1,026 / 39,600 ( 3 % )
9
    Total combinational functions : 879 / 39,600 ( 2 % )
10
    Dedicated logic registers : 622 / 39,600 ( 2 % )
11
Total registers : 622
12
Total pins : 24 / 129 ( 19 % )
13
Total virtual pins : 0
14
Total memory bits : 11,992 / 1,161,216 ( 1 % )
15
Embedded Multiplier 9-bit elements : 0 / 252 ( 0 % )
16
Total PLLs : 1 / 4 ( 25 % )

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.