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antiquity |
//author :Renliang Gu
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//Email: gurenliang@gmail.com
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//note: if there are some errors, please feel free to contact me. Thank you very much!
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//Next step, add ff_data control to show the IP is busy
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//version 0.3, declared a new variable data_av, and use it to start sending frame.
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//version 0.3, delete the usage of pre_buf, and rename the pre to preaddlt
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//version 0.3, add the option of frameID mode, by include common.v and judge the macro-varible frameIDfromRx
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//This module is used to receive data from the demodulate module and send the data to the Ethernet PHY chip
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`include "common.v"
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`define tx_crc_offset (`data_offset+((`uframelen+8)*`num_uframe/4)+2) //index of first bit of crc
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`define tx_total_len (`tx_crc_offset + (4<<1))
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`define txdata_len (((`uframelen+8)*`num_uframe/4)+2)
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`define less_than_a_nibble 1 //0.25*8=2
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`define last_cycle_val 2 //0.25*8=2
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`define preaddlt_len (`data_offset<<2)
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module TxModule(reset, phy_txd, phy_txen, phy_txclk, phy_txer,
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ff_clk, ff_en, ff_data,
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`ifdef frameIDfromRx
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frameid,
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`endif
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start,
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test1, test2, test3, test4);
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parameter nibble_idx_len = (`tx_total_len<= 2)? 1 : (`tx_total_len<= 4)? 2 :
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(`tx_total_len<= 8)? 3 : (`tx_total_len<= 16)? 4 :
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(`tx_total_len<= 32)? 5 : (`tx_total_len<= 64)? 6 :
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(`tx_total_len<=128)? 7 : (`tx_total_len<=256)? 8 :
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(`tx_total_len<=512)? 9 : (`tx_total_len<=1024)? 10 :
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(`tx_total_len<=2048)? 11 : 12;
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parameter ff_idx_len = (`txdata_len<= 2)? 1 : (`txdata_len<= 4)? 2 :
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(`txdata_len<= 8)? 3 : (`txdata_len<= 16)? 4 :
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(`txdata_len<= 32)? 5 : (`txdata_len<= 64)? 6 :
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(`txdata_len<=128)? 7 : (`txdata_len<=256)? 8 :
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(`txdata_len<=512)? 9 : (`txdata_len<=1024)? 10 : 11;
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input phy_txclk, reset;
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input ff_clk, ff_en, ff_data; //ff_clk should be 207.83333KHz
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`ifdef frameIDfromRx
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input[`frameidlen-1:0] frameid; //get the frameid information from RxModule
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reg[`frameidlen-1:0] frameid_buf[0:1];
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`endif
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`ifdef frameIDcount
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reg[`frameidlen-1:0] frameid=0;
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`endif
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reg[`frameidlen-1:0] frameid_reg;
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input start; //decide whether should give out the "need-data" ethernet package
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output [3:0] phy_txd; //MII
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output phy_txen, phy_txer;
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output test1, test2, test3, test4;
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reg test1;//, test2, test3, test4;
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reg[3:0] phy_txd;
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reg phy_txen;
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reg[`preaddlt_len-1:0] preaddlt;
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reg[3:0] txdata_buf[0:`txdata_len*2-1]; //two buffer helps to step over different frame seamlessly
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reg[ff_idx_len:0] txdata_buf_reader_address;
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reg[nibble_idx_len-1:0] nibble_idx;
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wire data_av;
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reg Enable_Crc, Initialize_Crc; //declare the variables for the CRC module
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wire [3:0] Data_Crc;
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wire CrcError;
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wire [31:0] Crc;
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wire txIDX;
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reg[1:0] cycle;
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reg ffIDX, ffIDX1, ffIDX2;
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reg[ff_idx_len-1:0] ff_idx;
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reg[2:0] ff_d;
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// Declare state register
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reg [2:0]txState;
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parameter s_idle = 3'h0, s_preamble = 3'h1, s_address = 3'h2, s_data = 3'h3, s_crc =3'h4;
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assign test2 = txState[2];
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assign test3 = txState[1];
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assign test4 = txState[0];
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always @ (posedge ff_clk) begin //receive data from demodulate module every bit one by one
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if(ff_en & start) begin
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`ifdef frameIDfromRx
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if((ff_idx==0)&&(cycle==0)) frameid_buf[ffIDX] <= frameid;
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`endif
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cycle <= cycle + 1;
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if((cycle==3)||
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((cycle == `last_cycle_val-1)&&(ff_idx==(`txdata_len-1-`less_than_a_nibble)))) begin
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txdata_buf[ffIDX*`txdata_len+ff_idx] <= ({ff_data,ff_d}>>(3-cycle));
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if (ff_idx == (`txdata_len-1-`less_than_a_nibble)) begin
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ffIDX <= ~ffIDX;
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ff_idx <= 0;
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cycle <= 0;
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//every time a frame being sent, frameID increases one
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`ifdef frameIDcount
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frameid <= frameid + 1;
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`endif
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end
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else begin
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ff_idx <= ff_idx + 1;
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end
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end else begin
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ff_d <= {ff_data, ff_d[2:1]};
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end
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end
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else begin
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ff_idx <= 0;
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cycle <= 0;
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end
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end
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assign phy_txer = 1'b0;
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assign data_av = ffIDX1 ^ ffIDX2;
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assign txIDX = ~ffIDX;
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always @ (negedge phy_txclk) begin //state machine run to send out the MAC frame
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ffIDX2 <= ffIDX1;
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ffIDX1 <= ffIDX;
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end
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// Determine the next state
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always @ (negedge phy_txclk) begin //state machine run to send out the MAC frame
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if (reset)
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txState <= s_idle;
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else begin
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case (txState)
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s_idle: begin //wait to be trigged
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test1 <= ~test1;
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if(data_av) begin //once be trigged, prepare the data to send
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txState <= s_preamble;
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end
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else txState <= s_idle;
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end
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s_preamble: //send the preambles
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if(nibble_idx == `da_offset-1)
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txState <= s_address;
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else
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txState <= s_preamble;
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s_address: begin //send the destination address, source address and type
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if(nibble_idx== `data_offset-1)
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txState <= s_data;
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else
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txState <= s_address;
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end
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s_data: //send data to PHY, every time four bits, lower bits go first
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//test2 <= ~test2;
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if (nibble_idx == `tx_crc_offset-1)
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txState <= s_crc;
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else txState <= s_data;
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s_crc:
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if (nibble_idx == `tx_total_len-1)
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txState <= s_idle;
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else txState <= s_crc;
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default:
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txState <= s_idle;
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endcase
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end
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end
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always @ (negedge phy_txclk) begin //state machine run to send out the MAC frame
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if (reset)
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nibble_idx <= 0;
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else if(txState==s_idle)
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nibble_idx <= 0;
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else
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nibble_idx <= nibble_idx + 1;
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end
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always @ (negedge phy_txclk) begin //state machine run to send out the MAC frame
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if (reset)
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phy_txd <= 4'h0;
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else
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case (txState)
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s_idle: begin
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//already stored MAC preamble, dest address and source address from right to left.
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//decide whether should ask PC for new frame
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/*if(empty) preaddlt <= {16'h0008, `MAC_ADD, `PC_MAC_ADD, `Preamble};
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else*/
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`ifdef frameIDfromRx
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preaddlt <= {frameid_buf[txIDX], 16'h0000, `MAC_ADD, `PC_MAC_ADD, `Preamble};
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`endif
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`ifdef frameIDcount
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preaddlt <= {frameid, 16'h0000, `MAC_ADD, `PC_MAC_ADD, `Preamble};
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`endif
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end
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s_preamble:
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{preaddlt[`preaddlt_len-5:0], phy_txd} <= preaddlt;
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s_address: begin
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{preaddlt[`preaddlt_len-5:0], phy_txd} <= preaddlt;
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txdata_buf_reader_address <= (txIDX*(`txdata_len));
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end
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s_data: begin
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txdata_buf_reader_address <= (txIDX*(`txdata_len))+nibble_idx-`data_offset+1;
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phy_txd <= txdata_buf[txdata_buf_reader_address];
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end
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s_crc: begin
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phy_txd[3] <= ~Crc[28]; //Special, the usage of the CRC_Module
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phy_txd[2] <= ~Crc[29];
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phy_txd[1] <= ~Crc[30];
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phy_txd[0] <= ~Crc[31];
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end
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default:
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phy_txd <= 4'h0;
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endcase
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end
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always @ (negedge phy_txclk) begin //state machine run to send out the MAC frame
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if (reset)
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phy_txen <= 1'b0;
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else if((txState==s_preamble)||(txState==s_address)||(txState==s_data)||(txState==s_crc))
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phy_txen <= 1'b1;
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else
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phy_txen <= 1'b0;
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end
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always @ (negedge phy_txclk) begin //state machine run to send out the MAC frame
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if (reset)
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Initialize_Crc <= 1'b0;
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else if(txState==s_preamble)
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Initialize_Crc <= 1'b1; //prepare the CRC_Module for the following addresses
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else
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Initialize_Crc <= 1'b0;
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end
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always @ (negedge phy_txclk) begin //state machine run to send out the MAC frame
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if (reset)
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Enable_Crc <= 1'b0;
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else if((txState==s_address)||(txState==s_data))
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Enable_Crc <= 1'b1; //enable the CRC_Module
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else
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Enable_Crc <= 1'b0;
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end
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assign Data_Crc[0] = phy_txd[3]; //input prepare for CRC_Module
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assign Data_Crc[1] = phy_txd[2];
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assign Data_Crc[2] = phy_txd[1];
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assign Data_Crc[3] = phy_txd[0];
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// Connecting module Crc
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CRC_Module txcrc (.Clk(phy_txclk), .Reset(reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
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.Crc(Crc), .CrcError(CrcError));
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endmodule
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