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[/] [16x2_lcd_controller/] [trunk/] [demo/] [lcd16x2_ctrl_demo.vhd] - Blame information for rev 8

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Line No. Rev Author Line
1 4 stachelsau
-------------------------------------------------------------------------------
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-- Title      : Synthesizable demo for design "lcd16x2_ctrl"
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-- Project    : 
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-------------------------------------------------------------------------------
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-- File       : lcd16x2_ctrl_tb.vhd
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-- Author     :   <stachelsau@T420>
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-- Company    : 
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-- Created    : 2012-07-28
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-- Last update: 2012-07-29
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-- Platform   : 
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-- Standard   : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description: This demo writes writes a "hello world" to the display and
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-- interchanges both lines periodically.
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-------------------------------------------------------------------------------
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-- Copyright (c) 2012 
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Date        Version  Author  Description
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-- 2012-07-28  1.0      stachelsau      Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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-------------------------------------------------------------------------------
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entity lcd16x2_ctrl_demo is
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  port (
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    clk    : in  std_logic;
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    lcd_e  : out std_logic;
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    lcd_rs : out std_logic;
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    lcd_rw : out std_logic;
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    lcd_db : out std_logic_vector(7 downto 4));
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end entity lcd16x2_ctrl_demo;
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-------------------------------------------------------------------------------
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architecture behavior of lcd16x2_ctrl_demo is
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  -- 
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  signal timer : natural range 0 to 100000000 := 0;
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  signal switch_lines : std_logic := '0';
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  signal line1 : std_logic_vector(127 downto 0);
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  signal line2 : std_logic_vector(127 downto 0);
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  -- component generics
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  constant CLK_PERIOD_NS : positive := 10;  -- 100 Mhz
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  -- component ports
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  signal rst          : std_logic;
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  signal line1_buffer : std_logic_vector(127 downto 0);
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  signal line2_buffer : std_logic_vector(127 downto 0);
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begin  -- architecture behavior
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  -- component instantiation
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  DUT : entity work.lcd16x2_ctrl
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    generic map (
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      CLK_PERIOD_NS => CLK_PERIOD_NS)
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    port map (
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      clk          => clk,
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      rst          => rst,
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      lcd_e        => lcd_e,
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      lcd_rs       => lcd_rs,
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      lcd_rw       => lcd_rw,
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      lcd_db       => lcd_db,
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      line1_buffer => line1_buffer,
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      line2_buffer => line2_buffer);
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  rst <= '0';
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  -- see the display's datasheet for the character map
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  line1(127 downto 120) <= X"20";
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  line1(119 downto 112) <= X"20";
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  line1(111 downto 104) <= X"48";  -- H
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  line1(103 downto 96)  <= X"65";  -- e
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  line1(95 downto 88)   <= X"6c";  -- l
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  line1(87 downto 80)   <= X"6c";  -- l
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  line1(79 downto 72)   <= X"6f";  -- o
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  line1(71 downto 64)   <= X"20";
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  line1(63 downto 56)   <= X"57";  -- W
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  line1(55 downto 48)   <= X"6f";  -- o
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  line1(47 downto 40)   <= X"72";  -- r
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  line1(39 downto 32)   <= X"6c";  -- l
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  line1(31 downto 24)   <= X"64";  -- d
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  line1(23 downto 16)   <= X"21";  -- !
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  line1(15 downto 8)    <= X"20";
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  line1(7 downto 0)     <= X"20";
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  line2(127 downto 120) <= X"30";
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  line2(119 downto 112) <= X"31";
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  line2(111 downto 104) <= X"32";
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  line2(103 downto 96)  <= X"33";
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  line2(95 downto 88)   <= X"34";
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  line2(87 downto 80)   <= X"35";
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  line2(79 downto 72)   <= X"36";
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  line2(71 downto 64)   <= X"37";
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  line2(63 downto 56)   <= X"38";
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  line2(55 downto 48)   <= X"39";
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  line2(47 downto 40)   <= X"3a";
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  line2(39 downto 32)   <= X"3b";
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  line2(31 downto 24)   <= X"3c";
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  line2(23 downto 16)   <= X"3d";
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  line2(15 downto 8)    <= X"3e";
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  line2(7 downto 0)     <= X"3f";
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  line1_buffer <= line2 when switch_lines = '1' else line1;
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  line2_buffer <= line1 when switch_lines = '1' else line2;
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  -- switch lines every second
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  process(clk)
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  begin
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    if rising_edge(clk) then
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      if timer = 0 then
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        timer <= 100000000;
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        switch_lines <= not switch_lines;
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      else
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        timer <= timer - 1;
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      end if;
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    end if;
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  end process;
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end architecture behavior;
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