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//---------------------------------------------------------------------------
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// File : tri_mode_ethernet_mac_0_support_resets.v
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// Author : Xilinx Inc.
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// -----------------------------------------------------------------------------
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// (c) Copyright 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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// -----------------------------------------------------------------------------
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// Description: This module holds the shared resets for the IDELAYCTRL
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// and the MMCM
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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module tri_mode_ethernet_mac_0_support_resets
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(
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input glbl_rstn,
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input refclk,
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input idelayctrl_ready,
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output idelayctrl_reset_out,
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input gtx_clk,
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input gtx_dcm_locked,
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output gtx_mmcm_rst_out // The reset pulse for the MMCM.
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);
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wire glbl_rst;
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wire idelayctrl_reset_in; // Used to trigger reset_sync generation in refclk domain.
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wire idelayctrl_reset_sync; // Used to create a reset pulse in the IDELAYCTRL refclk domain.
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reg [3:0] idelay_reset_cnt; // Counter to create a long IDELAYCTRL reset pulse.
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reg idelayctrl_reset;
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wire gtx_mmcm_rst_in;
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wire gtx_dcm_locked_int;
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wire gtx_dcm_locked_sync;
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reg gtx_dcm_locked_reg = 1;
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reg gtx_dcm_locked_edge = 1;
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assign glbl_rst = !glbl_rstn;
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//----------------------------------------------------------------------------
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// Reset circuitry associated with the IDELAYCTRL
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//----------------------------------------------------------------------------
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assign idelayctrl_reset_out = idelayctrl_reset;
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assign idelayctrl_reset_in = glbl_rst || !idelayctrl_ready;
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// Create a synchronous reset in the IDELAYCTRL refclk clock domain.
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tri_mode_ethernet_mac_0_reset_sync idelayctrl_reset_gen (
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.clk (refclk),
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.enable (1'b1),
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.reset_in (idelayctrl_reset_in),
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.reset_out (idelayctrl_reset_sync)
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);
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// Reset circuitry for the IDELAYCTRL reset.
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// The IDELAYCTRL must experience a pulse which is at least 50 ns in
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// duration. This is ten clock cycles of the 200MHz refclk. Here we
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// drive the reset pulse for 12 clock cycles.
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always @(posedge refclk)
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begin
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if (idelayctrl_reset_sync) begin
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idelay_reset_cnt <= 4'b0000;
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idelayctrl_reset <= 1'b1;
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end
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else begin
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case (idelay_reset_cnt)
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4'b0000 : idelay_reset_cnt <= 4'b0001;
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4'b0001 : idelay_reset_cnt <= 4'b0010;
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4'b0010 : idelay_reset_cnt <= 4'b0011;
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4'b0011 : idelay_reset_cnt <= 4'b0100;
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4'b0100 : idelay_reset_cnt <= 4'b0101;
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4'b0101 : idelay_reset_cnt <= 4'b0110;
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4'b0110 : idelay_reset_cnt <= 4'b0111;
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4'b0111 : idelay_reset_cnt <= 4'b1000;
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4'b1000 : idelay_reset_cnt <= 4'b1001;
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4'b1001 : idelay_reset_cnt <= 4'b1010;
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4'b1010 : idelay_reset_cnt <= 4'b1011;
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4'b1011 : idelay_reset_cnt <= 4'b1100;
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default : idelay_reset_cnt <= 4'b1100;
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endcase
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if (idelay_reset_cnt == 4'b1100) begin
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idelayctrl_reset <= 1'b0;
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end
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else begin
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idelayctrl_reset <= 1'b1;
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end
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end
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end
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//----------------------------------------------------------------------------
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// Reset circuitry associated with the MMCM
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//----------------------------------------------------------------------------
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assign gtx_mmcm_rst_in = glbl_rst | gtx_dcm_locked_edge;
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// Synchronise the async dcm_locked into the gtx_clk clock domain
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tri_mode_ethernet_mac_0_sync_block lock_sync (
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.clk (gtx_clk),
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.data_in (gtx_dcm_locked),
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.data_out (gtx_dcm_locked_sync)
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);
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// for the falling edge detect we want to force this at power on so init the flop to 1
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always @(posedge gtx_clk)
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begin
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gtx_dcm_locked_reg <= gtx_dcm_locked_sync;
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gtx_dcm_locked_edge <= gtx_dcm_locked_reg & !gtx_dcm_locked_sync;
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end
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// the MMCM reset should be at least 5ns - that is one cycle of the input clock -
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// since the source of the input reset is unknown (a push switch in board design)
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// this needs to be debounced
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tri_mode_ethernet_mac_0_reset_sync gtx_mmcm_reset_gen (
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.clk (gtx_clk),
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.enable (1'b1),
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.reset_in (gtx_mmcm_rst_in),
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.reset_out (gtx_mmcm_rst_out)
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);
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endmodule
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