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kuzmi4 |
// base: tri_mode_ethernet_mac_0_axi_lite_sm
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#include <stdio.h>
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#include "xil_io.h"
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//#include "xstatus.h"
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#include "tri_mode_emac.h"
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#define TMEMAC_MDIO_TOUT (0x1FFFFFFF)
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#define TMEMAC_AN_TOUT (0x1FFFFFFF)
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// KC705 Evaluation Board Features:
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// ..On power-up, or on reset, the PHY is configured to operate in GMII mode with PHY address
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// 0b00111 using the settings shown in Table 1-17. These settings can be overwritten via
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// software commands passed over the MDIO interface.
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// {Table 1-17: Board Connections for PHY Configuration Pins}
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//
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// 88E1111Datasheet_Rev_J.pdf:
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// 2.3.4 Mode Switching
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// reg: 0_4, 0_1.12, 0_27.12,
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// HWCFG_MODE[3:0] == 1011
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//
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u32 u32_tmemac_base;// = XPAR_TMEMAC_0_BASEADDR;
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//
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int phy_addr;
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int phy_id1;
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int phy_id2;
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int phy_link_speed;
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int phy_duplex;
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/**/
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int tri_mode_emac_phy_cfg(void);
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int tri_mode_emac_phy_det(void);
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int tmemac_phy_rd_reg(u8 reg_addr);
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int tmemac_phy_wr_reg(u8 reg_addr, u16 reg_data);
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/**/
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int tri_mode_emac_init(tmemac_cfg_t *iv_tmemac_cfg)
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{
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// dec vars
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int Value;
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// wr base
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u32_tmemac_base = iv_tmemac_cfg->base;
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// -> STARTUP
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Xil_Out32(u32_tmemac_base+CONFIG_MANAGEMENT_ADD, (1 << 6) | (24)); // MDIO Enable[6], Clock Divide[5:0]
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// -> UPDATE_SPEED
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Value = Xil_In32(u32_tmemac_base+SPEED_CONFIG_ADD);
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if (Value == 0) {
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Xil_Out32(+SPEED_CONFIG_ADD, (2 << 30)); // 2'b10 == 1Gbps,
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}
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//xil_printf("ms=%x\n", Xil_In32(u32_tmemac_base+SPEED_CONFIG_ADD));
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// PHY cfg
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Value = tri_mode_emac_phy_cfg();
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if (Value < 0) {
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return Value;
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}
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// Reseting MAC RX
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Xil_Out32(u32_tmemac_base+RECEIVER_ADD, (1 << 31) | (1 << 28)); // Reset, Receiver Enable
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// Reseting MAC TX
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Xil_Out32(u32_tmemac_base+TRANSMITTER_ADD, (1 << 31) | (1 << 28)); // Reset, Transmit Enable
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// Disabling Flow control
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Xil_Out32(u32_tmemac_base+CONFIG_FLOW_CTRL_ADD, 0);
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// Configuring unicast address
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Xil_Out32(u32_tmemac_base+CONFIG_UNI1_CTRL_ADD, iv_tmemac_cfg->mac_high); // high word
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Xil_Out32(u32_tmemac_base+CONFIG_UNI0_CTRL_ADD, iv_tmemac_cfg->mac_low); // low ..
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// Setting core to promiscuous mode
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Xil_Out32(u32_tmemac_base+CONFIG_ADDR_CTRL_ADD, (1 << 31));
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// Final
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return 0;
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}
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int tri_mode_emac_phy_cfg(void)
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{
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#ifndef MSIM
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// dec vars
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int Value;
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u32 x;
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// PHY det
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if (tri_mode_emac_phy_det()) {
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return -1;
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}
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// further phy-cfg:
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// TSE_PHY_MDIO_1000BASE_T_CTRL
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if (tmemac_phy_wr_reg(TSE_PHY_MDIO_1000BASE_T_CTRL, 1 << 9)) { // 1G Full-Duplex
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return -2;
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}
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// TSE_PHY_MDIO_ADV
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if (tmemac_phy_wr_reg(TSE_PHY_MDIO_ADV, (1 << 8) | (1 << 6))) { // 100M Full-Duplex, 10M Full-Duplex
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return -3;
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}
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// HWCFG_MODE[3:0] == RGMII
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Value = tmemac_phy_rd_reg(MRVL_PHY_MDIO_ESPEC_STS);
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Value &= ~(0x0F);
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Value |= MARVELL_PHY_RGMII; // [3:0] == 1011
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if (tmemac_phy_wr_reg(MRVL_PHY_MDIO_ESPEC_STS, Value)) {
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return -4;
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}
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// add/remove the clock delay
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Value = tmemac_phy_rd_reg(MRVL_PHY_MDIO_ESPEC_CTRL);
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Value &= ~((1 << 7) | (1 << 1));
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Value |= (1 << 7) | (0 << 1); // tri_mode_ethernet_mac_0_axi_lite_sm.v, MDIO_DELAY_RD_POLL
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if (tmemac_phy_wr_reg(MRVL_PHY_MDIO_ESPEC_CTRL, Value)) {
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return -5;
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}
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// set autoneg and reset
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Value = (1 << 15) | (1 << 12); // bit15: software reset, bit12 : AN enable (set after power up)
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if (tmemac_phy_wr_reg(TSE_PHY_MDIO_CONTROL, Value)) {
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return -6;
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}
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// w8 4 rst-low
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x = 0;
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do {
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Value = tmemac_phy_rd_reg(TSE_PHY_MDIO_CONTROL);
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if (++x == TMEMAC_AN_TOUT) {
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return -7;
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}
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} while((Value & (1 << 15)) == 1); // .. When the reset operation is done, this bit is cleared to 0 automatically.
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//xil_printf(" [phy_rst ] reg 0_0 = 0x%04x\n\r", Value);
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// Wait for Autonegotiation to complete
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x = 0;
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do {
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// useful ibala
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{
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volatile int wait;
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for (wait=0; wait < 100000; wait++);
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for (wait=0; wait < 100000; wait++);
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}
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//
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Value = tmemac_phy_rd_reg(TSE_PHY_MDIO_STATUS);
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if (Value == -1) {
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return -8;
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}
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//
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if (++x == TMEMAC_AN_TOUT) {
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xil_printf("ERR: Auto-Negotiation FAILED, STATUS: 0x%04x\n\r", tmemac_phy_rd_reg(TSE_PHY_MDIO_STATUS));
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return -9;
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}
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} while((Value & (1 << 5)) == 0);
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xil_printf(" [phy_rst ] OK, reg 0_1 = 0x%04x\n\r", Value);
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// get PHY-{Speed+Duplex}
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Value = tmemac_phy_rd_reg(MRVL_PHY_MDIO_SPEC_STS_C);
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if (Value == -1) {
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return -10;
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}
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//xil_printf("reg 0_17 = 0x%04x\n", Value);
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phy_duplex = Value && (1 << 13);
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phy_link_speed = (Value && (1 << 15))? 1000 :
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(Value && (1 << 14))? 100 :
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10 ;
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xil_printf(" [phy_cfg ] Speed is 0x%x Full Duplex is %x\n\r", phy_link_speed, phy_duplex);
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#else
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phy_link_speed = 1000;
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phy_duplex = 1;
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printf(" [phy_init] MSIM: found Marvell 88E1111 PHY\n");
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printf(" [phy_cfg ] MSIM: Speed is %d Full Duplex is %d\n", phy_link_speed, phy_duplex);
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#endif // MSIM
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// Final
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return 0;
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}
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int tri_mode_emac_phy_det(void) // phy detection
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{
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for (phy_addr = 0; phy_addr < 32; phy_addr++) {
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// TSE_PHY_MDIO_PHY_ID1
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phy_id1 = tmemac_phy_rd_reg(TSE_PHY_MDIO_PHY_ID1);
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if (phy_id1 == -1) { return -1; }
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// TSE_PHY_MDIO_PHY_ID2
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phy_id2 = tmemac_phy_rd_reg(TSE_PHY_MDIO_PHY_ID2);
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if (phy_id2 == -1) { return -1; }
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// check
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if (phy_id1 != phy_id2) {
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//xil_printf(" [phy_init] phyID = 0x%02x 0x%04x 0x%04x\n", phy_addr, phy_id1, phy_id2);
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//
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if (MARVELL_PHY_ID_OK(phy_id1) & MARVELL_PHY_MODEL_OK(phy_id2)) {
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xil_printf(" [phy_init] found Marvell 88E1111 PHY\n\r");
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return 0;
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}
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//
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break;
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}
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}
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return -1;
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}
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int tmemac_phy_rd_reg(u8 reg_addr) // phy reg-read
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{
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u32 Value, j;
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// poll MDIO sts
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do {
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Value = Xil_In32(u32_tmemac_base+MDIO_CONTROL);
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if (++j == TMEMAC_MDIO_TOUT) {
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return -1;
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}
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} while((Value & (1 << 7)) == 0);// MDIO Control Word (0x504), [7] == MDIO ready: When set .. previous transaction has completed..
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// post RD-req
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Value = (phy_addr << 24) | // TX_PHYAD
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(reg_addr << 16) | // TX_REGAD
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(MDIO_OP_RD << 14) | // TX_OP
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(1 << 11); // Initiate
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Xil_Out32(u32_tmemac_base+MDIO_CONTROL, Value);
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// poll RD-resp
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do {
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Value = Xil_In32(u32_tmemac_base+MDIO_RX_DATA);
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if (++j == TMEMAC_MDIO_TOUT) {
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return -1;
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}
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} while((Value & (1 << 16)) == 0);
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// Final
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return (Value & 0x0000FFFF); // [15:0]
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}
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int tmemac_phy_wr_reg(u8 reg_addr, u16 reg_data) // phy reg-write
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{
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u32 Value, j;
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// poll MDIO sts
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do {
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Value = Xil_In32(u32_tmemac_base+MDIO_CONTROL);
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if (++j == TMEMAC_MDIO_TOUT) {
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return -1;
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}
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} while((Value & (1 << 7)) == 0);// MDIO Control Word (0x504), [7] == MDIO ready: When set .. previous transaction has completed..
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// put WR-data
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Xil_Out32(u32_tmemac_base+MDIO_TX_DATA, reg_data);
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// post WR-req
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Value = (phy_addr << 24) | // TX_PHYAD
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(reg_addr << 16) | // TX_REGAD
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(MDIO_OP_WR << 14) | // TX_OP
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(1 << 11); // Initiate
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Xil_Out32(u32_tmemac_base+MDIO_CONTROL, Value);
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// Final
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return 0;
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}
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