Subversion Repositories 1g_ethernet_dpi

//------------------------------------------------------------------------------

// File       : tri_mode_ethernet_mac_0_example_design_clock.v

// Author     : Xilinx Inc.

// -----------------------------------------------------------------------------

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// -----------------------------------------------------------------------------

// Description:  This block generates the clocking logic required for the

//               example design.

`timescale 1 ps/1 ps

module tri_mode_ethernet_mac_0_example_design_clocks

   (

   // differential clock inputs

   input          clk_in_p,

   input          clk_in_n,

   // asynchronous control/resets

   input          glbl_rst,

   output         dcm_locked,

   // clock outputs

   output         gtx_clk_bufg,

   output         refclk_bufg,

   output         s_axi_aclk

   );

   wire           clkin1;

   wire           mmcm_rst;

   wire           clkin1_bufg;

   wire           dcm_locked_int;

   wire           dcm_locked_sync;

   reg            dcm_locked_reg = 1;

   reg            dcm_locked_edge = 1;

  // Input buffering

  //------------------------------------

  IBUFDS clkin1_buf

   (.O  (clkin1),

    .I  (clk_in_p),

    .IB (clk_in_n));

  // route clkin1 through a BUFGCE for the MMCM reset generation logic

  BUFGCE bufg_clkin1 (.I(clkin1), .CE  (1'b1), .O(clkin1_bufg));

  // detect a falling edge on dcm_locked (after resyncing to this domain)

  tri_mode_ethernet_mac_0_sync_block lock_sync (

     .clk              (clkin1_bufg),

     .data_in          (dcm_locked_int),

     .data_out         (dcm_locked_sync)

  );

  // for the falling edge detect we want to force this at power on so init the flop to 1

  always @(posedge clkin1_bufg)

  begin

     dcm_locked_reg     <= dcm_locked_sync;

     dcm_locked_edge    <= dcm_locked_reg & !dcm_locked_sync;

  end

  // the MMCM reset should be at least 5ns - that is one cycle of the input clock -

  // since the source of the input reset is unknown (a push switch in board design)

  // this needs to be debounced

   tri_mode_ethernet_mac_0_reset_sync mmcm_reset_gen (

      .clk              (clkin1_bufg),

      .enable           (1'b1),

      .reset_in         (glbl_rst | dcm_locked_edge),

      .reset_out        (mmcm_rst)

   );

  //----------------------------------------------------------------------------

  // Generate clocks using the clock wizard

  //----------------------------------------------------------------------------

  tri_mode_ethernet_mac_0_clk_wiz clock_generator

  (

      // Clock in ports

      .CLK_IN1       (clkin1),

      // Clock out ports

      .CLK_OUT1      (gtx_clk_bufg),

      .CLK_OUT2      (s_axi_aclk),

      .CLK_OUT3      (refclk_bufg),

      // Status and control signals

      .RESET         (mmcm_rst),

      .LOCKED        (dcm_locked_int)

 );

 assign dcm_locked = dcm_locked_int;

endmodule