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[/] [1g_ethernet_dpi/] [tags/] [v0.0/] [sw/] [dev/] [test_main/] [src/] [_hdl/] [bsp/] [include/] [xil_cache.h] - Blame information for rev 3

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/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_cache.h
*
* This header file contains cache related driver functions (or macros)
* that can be used to access the device.  The user should refer to the
* hardware device specification for more details of the device operation.
* The functions in this header file can be used across all Xilinx supported
* processors.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver   Who  Date     Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00  hbm  07/28/09 Initial release
* 3.02a sdm  10/24/11 Updated the file to include xparameters.h so that
*                     the correct cache flush routines are used based on
*                     whether the write-back or write-through caches are
*                     used (cr #630532).
* 3.10a asa  05/04/13 This version of MicroBlaze BSP adds support for system
*                                         cache/L2 cache. The existing/old APIs/macros in this
*                                         file are renamed to imply that they deal with L1 cache.
*                                         New macros/APIs are added to address similar features for
*                                         L2 cache. Users can include this file in their application
*                                         to use the various cache related APIs. These changes are
*                                         done for implementing PR #697214.
*
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
 
#ifndef XIL_CACHE_H
#define XIL_CACHE_H
 
#if defined XENV_VXWORKS
/* VxWorks environment */
#error "Unknown processor / architecture. Must be PPC for VxWorks."
#else
/* standalone environment */
 
//#include "mb_interface.h"
#include "xil_types.h"
#include "xparameters.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
/****************************************************************************/
/**
*
* Invalidate the entire L1 data cache. If the cacheline is modified (dirty),
* the modified contents are lost.
*
* @param    None.
*
* @return   None.
*
* @note
*
* Processor must be in real mode.
****************************************************************************/
#define Xil_L1DCacheInvalidate() //microblaze_invalidate_dcache()
 
/****************************************************************************/
/**
*
* Invalidate the entire L2 data cache. If the cacheline is modified (dirty),
* the modified contents are lost.
*
* @param    None.
*
* @return   None.
*
* @note
*
* Processor must be in real mode.
****************************************************************************/
#define Xil_L2CacheInvalidate() //microblaze_invalidate_cache_ext()
 
/****************************************************************************/
/**
*
* Invalidate the L1 data cache for the given address range.
* If the bytes specified by the address (Addr) are cached by the L1 data cache,
* the cacheline containing that byte is invalidated.  If the cacheline
* is modified (dirty), the modified contents are lost.
*
* @param    Addr is address of ragne to be invalidated.
* @param    Len is the length in bytes to be invalidated.
*
* @return   None.
*
* @note
*
* Processor must be in real mode.
****************************************************************************/
#define Xil_L1DCacheInvalidateRange(Addr, Len) /*\
                        microblaze_invalidate_dcache_range((Addr), (Len))*/
 
/****************************************************************************/
/**
*
* Invalidate the L1 data cache for the given address range.
* If the bytes specified by the address (Addr) are cached by the L1 data cache,
* the cacheline containing that byte is invalidated.  If the cacheline
* is modified (dirty), the modified contents are lost.
*
* @param    Addr is address of ragne to be invalidated.
* @param    Len is the length in bytes to be invalidated.
*
* @return   None.
*
* @note
*
* Processor must be in real mode.
****************************************************************************/
#define Xil_L2CacheInvalidateRange(Addr, Len) /*\
                microblaze_invalidate_cache_ext_range((Addr), (Len))*/
 
/****************************************************************************/
/**
* Flush the L1 data cache for the given address range.
* If the bytes specified by the address (Addr) are cached by the data cache,
* and is modified (dirty), the cacheline will be written to system memory.
* The cacheline will also be invalidated.
*
* @param    Addr is the starting address of the range to be flushed.
* @param    Len is the length in byte to be flushed.
*
* @return   None.
*
****************************************************************************/
#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
#   define Xil_L1DCacheFlushRange(Addr, Len) /*\
                microblaze_flush_dcache_range((Addr), (Len))*/
#else
#   define Xil_L1DCacheFlushRange(Addr, Len) /*\
                microblaze_invalidate_dcache_range((Addr), (Len))*/
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */
 
/****************************************************************************/
/**
* Flush the L2 data cache for the given address range.
* If the bytes specified by the address (Addr) are cached by the data cache,
* and is modified (dirty), the cacheline will be written to system memory.
* The cacheline will also be invalidated.
*
* @param    Addr is the starting address of the range to be flushed.
* @param    Len is the length in byte to be flushed.
*
* @return   None.
*
****************************************************************************/
#define Xil_L2CacheFlushRange(Addr, Len) /*\
                microblaze_flush_cache_ext_range((Addr), (Len))*/
 
/****************************************************************************/
/**
* Flush the entire L1 data cache. If any cacheline is dirty, the cacheline will be
* written to system memory. The entire data cache will be invalidated.
*
* @return   None.
*
* @note
*
****************************************************************************/
#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
#   define Xil_L1DCacheFlush() microblaze_flush_dcache()
#else
#   define Xil_L1DCacheFlush() //microblaze_invalidate_dcache()
#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */
 
/****************************************************************************/
/**
* Flush the entire L2 data cache. If any cacheline is dirty, the cacheline will be
* written to system memory. The entire data cache will be invalidated.
*
* @return   None.
*
* @note
*
****************************************************************************/
#define Xil_L2CacheFlush() //microblaze_flush_cache_ext()
 
/****************************************************************************/
/**
*
* Invalidate the instruction cache for the given address range.
*
* @param    Addr is address of ragne to be invalidated.
* @param    Len is the length in bytes to be invalidated.
*
* @return   None.
*
****************************************************************************/
#define Xil_L1ICacheInvalidateRange(Addr, Len) /*\
                        microblaze_invalidate_icache_range((Addr), (Len))*/
 
/****************************************************************************/
/**
*
* Invalidate the entire instruction cache.
*
* @param    None
*
* @return   None.
*
****************************************************************************/
#define Xil_L1ICacheInvalidate() /*\
                        microblaze_invalidate_icache()*/
 
 
/****************************************************************************/
/**
*
* Enable the L1 data cache.
*
* @return   None.
*
* @note     This is processor specific.
*
****************************************************************************/
#define Xil_L1DCacheEnable() /*\
                        microblaze_enable_dcache()*/
 
/****************************************************************************/
/**
*
* Disable the L1 data cache.
*
* @return   None.
*
* @note     This is processor specific.
*
****************************************************************************/
#define Xil_L1DCacheDisable() /*\
                        microblaze_disable_dcache()*/
 
/****************************************************************************/
/**
*
* Enable the instruction cache.
*
* @return   None.
*
* @note     This is processor specific.
*
****************************************************************************/
#define Xil_L1ICacheEnable() /*\
                        microblaze_enable_icache()*/
 
/****************************************************************************/
/**
*
* Disable the L1 Instruction cache.
*
* @return   None.
*
* @note     This is processor specific.
*
****************************************************************************/
#define Xil_L1ICacheDisable() /*\
                        microblaze_disable_icache()*/
 
/****************************************************************************/
/**
*
* Enable the data cache.
*
* @param    None
*
* @return   None.
*
****************************************************************************/
#define Xil_DCacheEnable() Xil_L1DCacheEnable()
 
/****************************************************************************/
/**
*
* Enable the instruction cache.
*
* @param    None
*
* @return   None.
*
* @note
*
*
****************************************************************************/
#define Xil_ICacheEnable() Xil_L1ICacheEnable()
 
/****************************************************************************
*
* Invalidate the entire Data cache.
*
* @param        None.
*
* @return       None.
*
* @note         None.
*
****************************************************************************/
#define Xil_DCacheInvalidate() \
        Xil_L2CacheInvalidate(); \
        Xil_L1DCacheInvalidate();
 
 
/****************************************************************************
*
* Invalidate the Data cache for the given address range.
* If the bytes specified by the address (adr) are cached by the Data cache,
* the cacheline containing that byte is invalidated.    If the cacheline
* is modified (dirty), the modified contents are lost and are NOT
* written to system memory before the line is invalidated.
*
* @param        Start address of ragne to be invalidated.
* @param        Length of range to be invalidated in bytes.
*
* @return       None.
*
* @note         None.
*
****************************************************************************/
#define Xil_DCacheInvalidateRange(Addr, Len) \
        Xil_L2CacheInvalidateRange((Addr), (Len)); \
        Xil_L1DCacheInvalidateRange((Addr), (Len));
 
 
/****************************************************************************
*
* Flush the entire Data cache.
*
* @param        None.
*
* @return       None.
*
* @note         None.
*
****************************************************************************/
#define Xil_DCacheFlush() \
        Xil_L2CacheFlush(); \
        Xil_L1DCacheFlush();
 
/****************************************************************************
* Flush the Data cache for the given address range.
* If the bytes specified by the address (adr) are cached by the Data cache,
* the cacheline containing that byte is invalidated.    If the cacheline
* is modified (dirty), the written to system memory first before the
* before the line is invalidated.
*
* @param        Start address of range to be flushed.
* @param        Length of range to be flushed in bytes.
*
* @return       None.
*
* @note         None.
*
****************************************************************************/
#define Xil_DCacheFlushRange(Addr, Len) \
        Xil_L2CacheFlushRange((Addr), (Len)); \
        Xil_L1DCacheFlushRange((Addr), (Len));
 
 
/****************************************************************************
*
* Invalidate the entire instruction cache.
*
* @param        None.
*
* @return       None.
*
* @note         None.
*
****************************************************************************/
#define Xil_ICacheInvalidate() \
        Xil_L2CacheInvalidate(); \
        Xil_L1ICacheInvalidate();
 
 
/****************************************************************************
*
* Invalidate the instruction cache for the given address range.
* If the bytes specified by the address (adr) are cached by the Data cache,
* the cacheline containing that byte is invalidated. If the cacheline
* is modified (dirty), the modified contents are lost and are NOT
* written to system memory before the line is invalidated.
*
* @param        Start address of ragne to be invalidated.
* @param        Length of range to be invalidated in bytes.
*
* @return       None.
*
* @note         None.
*
****************************************************************************/
#define Xil_ICacheInvalidateRange(Addr, Len) \
        Xil_L2CacheInvalidateRange((Addr), (Len)); \
        Xil_L1ICacheInvalidateRange((Addr), (Len));
 
void Xil_DCacheDisable(void);
void Xil_ICacheDisable(void);
 
#ifdef __cplusplus
}
#endif
 
#endif
 
#endif

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Subversion Repositories 1g_ethernet_dpi

[/] [1g_ethernet_dpi/] [tags/] [v0.0/] [sw/] [dev/] [test_main/] [src/] [_hdl/] [bsp/] [include/] [xil_cache.h] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	kuzmi4	`/******************************************************************************`
2			`*`
3			`* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.`
4			`*`
5			`* Permission is hereby granted, free of charge, to any person obtaining a copy`
6			`* of this software and associated documentation files (the "Software"), to deal`
7			`* in the Software without restriction, including without limitation the rights`
8			`* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell`
9			`* copies of the Software, and to permit persons to whom the Software is`
10			`* furnished to do so, subject to the following conditions:`
11			`*`
12			`* The above copyright notice and this permission notice shall be included in`
13			`* all copies or substantial portions of the Software.`
14			`*`
15			`* Use of the Software is limited solely to applications:`
16			`* (a) running on a Xilinx device, or`
17			`* (b) that interact with a Xilinx device through a bus or interconnect.`
18			`*`
19			`* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR`
20			`* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,`
21			`* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL`
22			`* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,`
23			`* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF`
24			`* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE`
25			`* SOFTWARE.`
26			`*`
27			`* Except as contained in this notice, the name of the Xilinx shall not be used`
28			`* in advertising or otherwise to promote the sale, use or other dealings in`
29			`* this Software without prior written authorization from Xilinx.`
30			`*`
31			`******************************************************************************/`
32			`/*****************************************************************************/`
33			`/**`
34			`*`
35			`* @file xil_cache.h`
36			`*`
37			`* This header file contains cache related driver functions (or macros)`
38			`* that can be used to access the device. The user should refer to the`
39			`* hardware device specification for more details of the device operation.`
40			`* The functions in this header file can be used across all Xilinx supported`
41			`* processors.`
42			`*`
43			`* <pre>`
44			`* MODIFICATION HISTORY:`
45			`*`
46			`* Ver Who Date Changes`
47			`* ----- ---- -------- -------------------------------------------------------`
48			`* 1.00 hbm 07/28/09 Initial release`
49			`* 3.02a sdm 10/24/11 Updated the file to include xparameters.h so that`
50			`* the correct cache flush routines are used based on`
51			`* whether the write-back or write-through caches are`
52			`* used (cr #630532).`
53			`* 3.10a asa 05/04/13 This version of MicroBlaze BSP adds support for system`
54			`* cache/L2 cache. The existing/old APIs/macros in this`
55			`* file are renamed to imply that they deal with L1 cache.`
56			`* New macros/APIs are added to address similar features for`
57			`* L2 cache. Users can include this file in their application`
58			`* to use the various cache related APIs. These changes are`
59			`* done for implementing PR #697214.`
60			`*`
61			`* </pre>`
62			`*`
63			`* @note`
64			`*`
65			`* None.`
66			`*`
67			`******************************************************************************/`
68
69			`#ifndef XIL_CACHE_H`
70			`#define XIL_CACHE_H`
71
72			`#if defined XENV_VXWORKS`
73			`/* VxWorks environment */`
74			`#error "Unknown processor / architecture. Must be PPC for VxWorks."`
75			`#else`
76			`/* standalone environment */`
77
78			`//#include "mb_interface.h"`
79			`#include "xil_types.h"`
80			`#include "xparameters.h"`
81
82			`#ifdef __cplusplus`
83			`extern "C" {`
84			`#endif`
85
86			`/****************************************************************************/`
87			`/**`
88			`*`
89			`* Invalidate the entire L1 data cache. If the cacheline is modified (dirty),`
90			`* the modified contents are lost.`
91			`*`
92			`* @param None.`
93			`*`
94			`* @return None.`
95			`*`
96			`* @note`
97			`*`
98			`* Processor must be in real mode.`
99			`****************************************************************************/`
100			`#define Xil_L1DCacheInvalidate() //microblaze_invalidate_dcache()`
101
102			`/****************************************************************************/`
103			`/**`
104			`*`
105			`* Invalidate the entire L2 data cache. If the cacheline is modified (dirty),`
106			`* the modified contents are lost.`
107			`*`
108			`* @param None.`
109			`*`
110			`* @return None.`
111			`*`
112			`* @note`
113			`*`
114			`* Processor must be in real mode.`
115			`****************************************************************************/`
116			`#define Xil_L2CacheInvalidate() //microblaze_invalidate_cache_ext()`
117
118			`/****************************************************************************/`
119			`/**`
120			`*`
121			`* Invalidate the L1 data cache for the given address range.`
122			`* If the bytes specified by the address (Addr) are cached by the L1 data cache,`
123			`* the cacheline containing that byte is invalidated. If the cacheline`
124			`* is modified (dirty), the modified contents are lost.`
125			`*`
126			`* @param Addr is address of ragne to be invalidated.`
127			`* @param Len is the length in bytes to be invalidated.`
128			`*`
129			`* @return None.`
130			`*`
131			`* @note`
132			`*`
133			`* Processor must be in real mode.`
134			`****************************************************************************/`
135			`#define Xil_L1DCacheInvalidateRange(Addr, Len) /*\`
136			`microblaze_invalidate_dcache_range((Addr), (Len))*/`
137
138			`/****************************************************************************/`
139			`/**`
140			`*`
141			`* Invalidate the L1 data cache for the given address range.`
142			`* If the bytes specified by the address (Addr) are cached by the L1 data cache,`
143			`* the cacheline containing that byte is invalidated. If the cacheline`
144			`* is modified (dirty), the modified contents are lost.`
145			`*`
146			`* @param Addr is address of ragne to be invalidated.`
147			`* @param Len is the length in bytes to be invalidated.`
148			`*`
149			`* @return None.`
150			`*`
151			`* @note`
152			`*`
153			`* Processor must be in real mode.`
154			`****************************************************************************/`
155			`#define Xil_L2CacheInvalidateRange(Addr, Len) /*\`
156			`microblaze_invalidate_cache_ext_range((Addr), (Len))*/`
157
158			`/****************************************************************************/`
159			`/**`
160			`* Flush the L1 data cache for the given address range.`
161			`* If the bytes specified by the address (Addr) are cached by the data cache,`
162			`* and is modified (dirty), the cacheline will be written to system memory.`
163			`* The cacheline will also be invalidated.`
164			`*`
165			`* @param Addr is the starting address of the range to be flushed.`
166			`* @param Len is the length in byte to be flushed.`
167			`*`
168			`* @return None.`
169			`*`
170			`****************************************************************************/`
171			`#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)`
172			`# define Xil_L1DCacheFlushRange(Addr, Len) /*\`
173			`microblaze_flush_dcache_range((Addr), (Len))*/`
174			`#else`
175			`# define Xil_L1DCacheFlushRange(Addr, Len) /*\`
176			`microblaze_invalidate_dcache_range((Addr), (Len))*/`
177			`#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */`
178
179			`/****************************************************************************/`
180			`/**`
181			`* Flush the L2 data cache for the given address range.`
182			`* If the bytes specified by the address (Addr) are cached by the data cache,`
183			`* and is modified (dirty), the cacheline will be written to system memory.`
184			`* The cacheline will also be invalidated.`
185			`*`
186			`* @param Addr is the starting address of the range to be flushed.`
187			`* @param Len is the length in byte to be flushed.`
188			`*`
189			`* @return None.`
190			`*`
191			`****************************************************************************/`
192			`#define Xil_L2CacheFlushRange(Addr, Len) /*\`
193			`microblaze_flush_cache_ext_range((Addr), (Len))*/`
194
195			`/****************************************************************************/`
196			`/**`
197			`* Flush the entire L1 data cache. If any cacheline is dirty, the cacheline will be`
198			`* written to system memory. The entire data cache will be invalidated.`
199			`*`
200			`* @return None.`
201			`*`
202			`* @note`
203			`*`
204			`****************************************************************************/`
205			`#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)`
206			`# define Xil_L1DCacheFlush() microblaze_flush_dcache()`
207			`#else`
208			`# define Xil_L1DCacheFlush() //microblaze_invalidate_dcache()`
209			`#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */`
210
211			`/****************************************************************************/`
212			`/**`
213			`* Flush the entire L2 data cache. If any cacheline is dirty, the cacheline will be`
214			`* written to system memory. The entire data cache will be invalidated.`
215			`*`
216			`* @return None.`
217			`*`
218			`* @note`
219			`*`
220			`****************************************************************************/`
221			`#define Xil_L2CacheFlush() //microblaze_flush_cache_ext()`
222
223			`/****************************************************************************/`
224			`/**`
225			`*`
226			`* Invalidate the instruction cache for the given address range.`
227			`*`
228			`* @param Addr is address of ragne to be invalidated.`
229			`* @param Len is the length in bytes to be invalidated.`
230			`*`
231			`* @return None.`
232			`*`
233			`****************************************************************************/`
234			`#define Xil_L1ICacheInvalidateRange(Addr, Len) /*\`
235			`microblaze_invalidate_icache_range((Addr), (Len))*/`
236
237			`/****************************************************************************/`
238			`/**`
239			`*`
240			`* Invalidate the entire instruction cache.`
241			`*`
242			`* @param None`
243			`*`
244			`* @return None.`
245			`*`
246			`****************************************************************************/`
247			`#define Xil_L1ICacheInvalidate() /*\`
248			`microblaze_invalidate_icache()*/`
249
250
251			`/****************************************************************************/`
252			`/**`
253			`*`
254			`* Enable the L1 data cache.`
255			`*`
256			`* @return None.`
257			`*`
258			`* @note This is processor specific.`
259			`*`
260			`****************************************************************************/`
261			`#define Xil_L1DCacheEnable() /*\`
262			`microblaze_enable_dcache()*/`
263
264			`/****************************************************************************/`
265			`/**`
266			`*`
267			`* Disable the L1 data cache.`
268			`*`
269			`* @return None.`
270			`*`
271			`* @note This is processor specific.`
272			`*`
273			`****************************************************************************/`
274			`#define Xil_L1DCacheDisable() /*\`
275			`microblaze_disable_dcache()*/`
276
277			`/****************************************************************************/`
278			`/**`
279			`*`
280			`* Enable the instruction cache.`
281			`*`
282			`* @return None.`
283			`*`
284			`* @note This is processor specific.`
285			`*`
286			`****************************************************************************/`
287			`#define Xil_L1ICacheEnable() /*\`
288			`microblaze_enable_icache()*/`
289
290			`/****************************************************************************/`
291			`/**`
292			`*`
293			`* Disable the L1 Instruction cache.`
294			`*`
295			`* @return None.`
296			`*`
297			`* @note This is processor specific.`
298			`*`
299			`****************************************************************************/`
300			`#define Xil_L1ICacheDisable() /*\`
301			`microblaze_disable_icache()*/`
302
303			`/****************************************************************************/`
304			`/**`
305			`*`
306			`* Enable the data cache.`
307			`*`
308			`* @param None`
309			`*`
310			`* @return None.`
311			`*`
312			`****************************************************************************/`
313			`#define Xil_DCacheEnable() Xil_L1DCacheEnable()`
314
315			`/****************************************************************************/`
316			`/**`
317			`*`
318			`* Enable the instruction cache.`
319			`*`
320			`* @param None`
321			`*`
322			`* @return None.`
323			`*`
324			`* @note`
325			`*`
326			`*`
327			`****************************************************************************/`
328			`#define Xil_ICacheEnable() Xil_L1ICacheEnable()`
329
330			`/****************************************************************************`
331			`*`
332			`* Invalidate the entire Data cache.`
333			`*`
334			`* @param None.`
335			`*`
336			`* @return None.`
337			`*`
338			`* @note None.`
339			`*`
340			`****************************************************************************/`
341			`#define Xil_DCacheInvalidate() \`
342			`Xil_L2CacheInvalidate(); \`
343			`Xil_L1DCacheInvalidate();`
344
345
346			`/****************************************************************************`
347			`*`
348			`* Invalidate the Data cache for the given address range.`
349			`* If the bytes specified by the address (adr) are cached by the Data cache,`
350			`* the cacheline containing that byte is invalidated. If the cacheline`
351			`* is modified (dirty), the modified contents are lost and are NOT`
352			`* written to system memory before the line is invalidated.`
353			`*`
354			`* @param Start address of ragne to be invalidated.`
355			`* @param Length of range to be invalidated in bytes.`
356			`*`
357			`* @return None.`
358			`*`
359			`* @note None.`
360			`*`
361			`****************************************************************************/`
362			`#define Xil_DCacheInvalidateRange(Addr, Len) \`
363			`Xil_L2CacheInvalidateRange((Addr), (Len)); \`
364			`Xil_L1DCacheInvalidateRange((Addr), (Len));`
365
366
367			`/****************************************************************************`
368			`*`
369			`* Flush the entire Data cache.`
370			`*`
371			`* @param None.`
372			`*`
373			`* @return None.`
374			`*`
375			`* @note None.`
376			`*`
377			`****************************************************************************/`
378			`#define Xil_DCacheFlush() \`
379			`Xil_L2CacheFlush(); \`
380			`Xil_L1DCacheFlush();`
381
382			`/****************************************************************************`
383			`* Flush the Data cache for the given address range.`
384			`* If the bytes specified by the address (adr) are cached by the Data cache,`
385			`* the cacheline containing that byte is invalidated. If the cacheline`
386			`* is modified (dirty), the written to system memory first before the`
387			`* before the line is invalidated.`
388			`*`
389			`* @param Start address of range to be flushed.`
390			`* @param Length of range to be flushed in bytes.`
391			`*`
392			`* @return None.`
393			`*`
394			`* @note None.`
395			`*`
396			`****************************************************************************/`
397			`#define Xil_DCacheFlushRange(Addr, Len) \`
398			`Xil_L2CacheFlushRange((Addr), (Len)); \`
399			`Xil_L1DCacheFlushRange((Addr), (Len));`
400
401
402			`/****************************************************************************`
403			`*`
404			`* Invalidate the entire instruction cache.`
405			`*`
406			`* @param None.`
407			`*`
408			`* @return None.`
409			`*`
410			`* @note None.`
411			`*`
412			`****************************************************************************/`
413			`#define Xil_ICacheInvalidate() \`
414			`Xil_L2CacheInvalidate(); \`
415			`Xil_L1ICacheInvalidate();`
416
417
418			`/****************************************************************************`
419			`*`
420			`* Invalidate the instruction cache for the given address range.`
421			`* If the bytes specified by the address (adr) are cached by the Data cache,`
422			`* the cacheline containing that byte is invalidated. If the cacheline`
423			`* is modified (dirty), the modified contents are lost and are NOT`
424			`* written to system memory before the line is invalidated.`
425			`*`
426			`* @param Start address of ragne to be invalidated.`
427			`* @param Length of range to be invalidated in bytes.`
428			`*`
429			`* @return None.`
430			`*`
431			`* @note None.`
432			`*`
433			`****************************************************************************/`
434			`#define Xil_ICacheInvalidateRange(Addr, Len) \`
435			`Xil_L2CacheInvalidateRange((Addr), (Len)); \`
436			`Xil_L1ICacheInvalidateRange((Addr), (Len));`
437
438			`void Xil_DCacheDisable(void);`
439			`void Xil_ICacheDisable(void);`
440
441			`#ifdef __cplusplus`
442			`}`
443			`#endif`
444
445			`#endif`
446
447			`#endif`