OpenCores
URL https://opencores.org/ocsvn/1g_ethernet_dpi/1g_ethernet_dpi/trunk

Subversion Repositories 1g_ethernet_dpi

[/] [1g_ethernet_dpi/] [trunk/] [hw/] [layout/] [bd/] [base_microblaze_design.bd] - Blame information for rev 4

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Line No. Rev Author Line
1 4 kuzmi4 

2
3 
 
4
5 
    xilinx.com
6 
    BlockDiagram
7 
    base_microblaze_design
8 
    1.00.a
9
10
11 
        isTop
12 
        true
13
14
15
16
17 
        led_8bits
18
19
20
21
22
23 
        rs232_uart
24
25
26
27
28
29 
        tmemac_1
30
31
32
33
34
35 
        CLK.CLK
36 
        Clk
37 
        Clock
38
39
40
41
42
43
44 
              CLK
45
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47 
              Clk
48
49
50
51
52
53 
            FREQ_HZ
54 
            100000000
55
56
57 
            ASSOCIATED_RESET
58 
            reset
59
60
61
62
63 
        RST.RESET
64 
        Reset
65 
        Reset
66
67
68
69
70
71
72 
              RST
73
74
75 
              reset
76
77
78
79
80
81 
            POLARITY
82 
            ACTIVE_HIGH
83
84
85
86
87
88
89
90 
          BlockDiagram
91 
          :vivado.xilinx.com:
92
93
94
95
96
97 
          Clk
98
99 
            in
100
101
102
103 
          reset
104
105 
            in
106
107
108
109
110
111 
 
112
113 
    xilinx.com
114 
    BlockDiagram
115 
    base_microblaze_design_imp
116 
    1.00.a
117
118
119 
        axi_gpio_0
120
121
122 
          base_microblaze_design_axi_gpio_0_0
123 
          true
124 
          led_8bits
125
126
127
128 
        axi_uartlite_0
129
130
131 
          base_microblaze_design_axi_uartlite_0_0
132 
          115200
133 
          true
134 
          rs232_uart
135
136
137
138 
        tri_mode_emac_0
139
140
141 
          base_microblaze_design_tri_mode_emac_0_0
142
143
144
145 
        microblaze_0
146
147
148 
          base_microblaze_design_microblaze_0_0
149 
          1
150 
          1
151 
          1
152 
          1
153 
          1
154 
          1
155 
          1
156 
          1
157 
          1
158
159
160
161 
        microblaze_0_local_memory
162
163
164
165 
        mdm_1
166
167
168 
          base_microblaze_design_mdm_1_0
169
170
171
172 
        rst_Clk_100M
173
174
175 
          base_microblaze_design_rst_Clk_100M_0
176
177
178
179 
        microblaze_0_axi_periph
180
181
182 
          base_microblaze_design_microblaze_0_axi_periph_0
183 
          3
184 
          6
185 
          xilinx.com:ip:axi_interconnect:2.1
186
187
188
189 
        axi_dma_0
190
191
192 
          base_microblaze_design_axi_dma_0_0
193 
          0
194 
          1
195 
          8
196
197
198
199 
        blk_mem_gen_0
200
201
202 
          base_microblaze_design_blk_mem_gen_0_0
203 
          True_Dual_Port_RAM
204 
          true
205 
          Use_ENB_Pin
206 
          true
207 
          100
208 
          50
209 
          100
210
211
212
213 
        axi_bram_ctrl_0
214
215
216 
          base_microblaze_design_axi_bram_ctrl_0_0
217
218
219
220 
        axi_intc_0
221
222
223 
          base_microblaze_design_axi_intc_0_0
224
225
226
227 
        xlconcat_0
228
229
230 
          base_microblaze_design_xlconcat_0_0
231
232
233
234
235
236 
        microblaze_0_dlmb_1
237
238
239
240
241 
        microblaze_0_ilmb_1
242
243
244
245
246 
        microblaze_0_debug
247
248
249
250
251 
        microblaze_0_M_AXI_DP
252
253
254
255
256 
        microblaze_0_axi_periph_M00_AXI
257
258
259
260
261 
        microblaze_0_axi_periph_M01_AXI
262
263
264
265
266 
        microblaze_0_axi_periph_M02_AXI
267
268
269
270
271 
        microblaze_0_axi_periph_M03_AXI
272
273
274
275
276 
        axi_dma_0_M_AXIS_MM2S
277
278
279
280
281 
        tri_mode_emac_0_rx_axis_fifo
282
283
284
285
286 
        axi_bram_ctrl_0_BRAM_PORTA
287
288
289
290
291 
        axi_bram_ctrl_0_BRAM_PORTB
292
293
294
295
296 
        microblaze_0_axi_periph_M04_AXI
297
298
299
300
301 
        axi_dma_0_M_AXI_MM2S
302
303
304
305
306 
        axi_dma_0_M_AXI_S2MM
307
308
309
310
311 
        microblaze_0_axi_periph_M05_AXI
312
313
314
315
316 
        axi_intc_0_interrupt
317
318
319
320
321
322
323 
        microblaze_0_Clk
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350 
        rst_Clk_100M_mb_reset
351
352
353
354
355 
        rst_Clk_100M_bus_struct_reset
356
357
358
359
360 
        mdm_1_debug_sys_rst
361
362
363
364
365 
        reset_1
366
367
368
369
370 
        rst_Clk_100M_peripheral_aresetn1
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393 
        rst_Clk_100M_interconnect_aresetn
394
395
396
397
398 
        xlconcat_0_dout
399
400
401
402
403 
        axi_dma_0_mm2s_introut
404
405
406
407
408 
        axi_dma_0_s2mm_introut
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425 
 
426
427 
    xilinx.com
428 
    BlockDiagram/base_microblaze_design_imp
429 
    microblaze_0_axi_periph
430 
    1.00.a
431
432
433 
        S00_AXI
434
435
436
437
438
439 
        M00_AXI
440
441
442
443
444
445 
        M01_AXI
446
447
448
449
450
451 
        M02_AXI
452
453
454
455
456
457 
        M03_AXI
458
459
460
461
462
463 
        M04_AXI
464
465
466
467
468
469 
        S01_AXI
470
471
472
473
474
475 
        S02_AXI
476
477
478
479
480
481 
        M05_AXI
482
483
484
485
486
487 
        CLK.ACLK
488 
        Clk
489 
        Clock
490
491
492
493
494
495
496 
              CLK
497
498
499 
              ACLK
500
501
502
503
504
505 
        RST.ARESETN
506 
        Reset
507 
        Reset
508
509
510
511
512
513
514 
              RST
515
516
517 
              ARESETN
518
519
520
521
522
523 
        CLK.S00_ACLK
524 
        Clk
525 
        Clock
526
527
528
529
530
531
532 
              CLK
533
534
535 
              S00_ACLK
536
537
538
539
540
541 
            ASSOCIATED_BUSIF
542 
            S00_AXI
543
544
545 
            ASSOCIATED_RESET
546 
            S00_ARESETN
547
548
549
550
551 
        RST.S00_ARESETN
552 
        Reset
553 
        Reset
554
555
556
557
558
559
560 
              RST
561
562
563 
              S00_ARESETN
564
565
566
567
568
569 
        CLK.M00_ACLK
570 
        Clk
571 
        Clock
572
573
574
575
576
577
578 
              CLK
579
580
581 
              M00_ACLK
582
583
584
585
586
587 
            ASSOCIATED_BUSIF
588 
            M00_AXI
589
590
591 
            ASSOCIATED_RESET
592 
            M00_ARESETN
593
594
595
596
597 
        RST.M00_ARESETN
598 
        Reset
599 
        Reset
600
601
602
603
604
605
606 
              RST
607
608
609 
              M00_ARESETN
610
611
612
613
614
615 
        CLK.M01_ACLK
616 
        Clk
617 
        Clock
618
619
620
621
622
623
624 
              CLK
625
626
627 
              M01_ACLK
628
629
630
631
632
633 
            ASSOCIATED_BUSIF
634 
            M01_AXI
635
636
637 
            ASSOCIATED_RESET
638 
            M01_ARESETN
639
640
641
642
643 
        RST.M01_ARESETN
644 
        Reset
645 
        Reset
646
647
648
649
650
651
652 
              RST
653
654
655 
              M01_ARESETN
656
657
658
659
660
661 
        CLK.M02_ACLK
662 
        Clk
663 
        Clock
664
665
666
667
668
669
670 
              CLK
671
672
673 
              M02_ACLK
674
675
676
677
678
679 
            ASSOCIATED_BUSIF
680 
            M02_AXI
681
682
683 
            ASSOCIATED_RESET
684 
            M02_ARESETN
685
686
687
688
689 
        RST.M02_ARESETN
690 
        Reset
691 
        Reset
692
693
694
695
696
697
698 
              RST
699
700
701 
              M02_ARESETN
702
703
704
705
706
707 
        CLK.M03_ACLK
708 
        Clk
709 
        Clock
710
711
712
713
714
715
716 
              CLK
717
718
719 
              M03_ACLK
720
721
722
723
724
725 
            ASSOCIATED_BUSIF
726 
            M03_AXI
727
728
729 
            ASSOCIATED_RESET
730 
            M03_ARESETN
731
732
733
734
735 
        RST.M03_ARESETN
736 
        Reset
737 
        Reset
738
739
740
741
742
743
744 
              RST
745
746
747 
              M03_ARESETN
748
749
750
751
752
753 
        CLK.M04_ACLK
754 
        Clk
755 
        Clock
756
757
758
759
760
761
762 
              CLK
763
764
765 
              M04_ACLK
766
767
768
769
770
771 
            ASSOCIATED_BUSIF
772 
            M04_AXI
773
774
775 
            ASSOCIATED_RESET
776 
            M04_ARESETN
777
778
779
780
781 
        RST.M04_ARESETN
782 
        Reset
783 
        Reset
784
785
786
787
788
789
790 
              RST
791
792
793 
              M04_ARESETN
794
795
796
797
798
799 
        CLK.S01_ACLK
800 
        Clk
801 
        Clock
802
803
804
805
806
807
808 
              CLK
809
810
811 
              S01_ACLK
812
813
814
815
816
817 
            ASSOCIATED_BUSIF
818 
            S01_AXI
819
820
821 
            ASSOCIATED_RESET
822 
            S01_ARESETN
823
824
825
826
827 
        RST.S01_ARESETN
828 
        Reset
829 
        Reset
830
831
832
833
834
835
836 
              RST
837
838
839 
              S01_ARESETN
840
841
842
843
844
845 
        CLK.S02_ACLK
846 
        Clk
847 
        Clock
848
849
850
851
852
853
854 
              CLK
855
856
857 
              S02_ACLK
858
859
860
861
862
863 
            ASSOCIATED_BUSIF
864 
            S02_AXI
865
866
867 
            ASSOCIATED_RESET
868 
            S02_ARESETN
869
870
871
872
873 
        RST.S02_ARESETN
874 
        Reset
875 
        Reset
876
877
878
879
880
881
882 
              RST
883
884
885 
              S02_ARESETN
886
887
888
889
890
891 
        CLK.M05_ACLK
892 
        Clk
893 
        Clock
894
895
896
897
898
899
900 
              CLK
901
902
903 
              M05_ACLK
904
905
906
907
908
909 
            ASSOCIATED_BUSIF
910 
            M05_AXI
911
912
913 
            ASSOCIATED_RESET
914 
            M05_ARESETN
915
916
917
918
919 
        RST.M05_ARESETN
920 
        Reset
921 
        Reset
922
923
924
925
926
927
928 
              RST
929
930
931 
              M05_ARESETN
932
933
934
935
936
937
938
939
940 
          BlockDiagram
941 
          :vivado.xilinx.com:
942
943
944
945
946
947 
          ACLK
948
949 
            in
950
951
952
953 
          ARESETN
954
955 
            in
956
957 
              0
958 
              0
959
960
961
962
963 
          S00_ACLK
964
965 
            in
966
967
968
969 
          S00_ARESETN
970
971 
            in
972
973 
              0
974 
              0
975
976
977
978
979 
          M00_ACLK
980
981 
            in
982
983
984
985 
          M00_ARESETN
986
987 
            in
988
989 
              0
990 
              0
991
992
993
994
995 
          M01_ACLK
996
997 
            in
998
999
1000
1001 
          M01_ARESETN
1002
1003 
            in
1004
1005 
              0
1006 
              0
1007
1008
1009
1010
1011 
          M02_ACLK
1012
1013 
            in
1014
1015
1016
1017 
          M02_ARESETN
1018
1019 
            in
1020
1021 
              0
1022 
              0
1023
1024
1025
1026
1027 
          M03_ACLK
1028
1029 
            in
1030
1031
1032
1033 
          M03_ARESETN
1034
1035 
            in
1036
1037 
              0
1038 
              0
1039
1040
1041
1042
1043 
          M04_ACLK
1044
1045 
            in
1046
1047
1048
1049 
          M04_ARESETN
1050
1051 
            in
1052
1053 
              0
1054 
              0
1055
1056
1057
1058
1059 
          S01_ACLK
1060
1061 
            in
1062
1063
1064
1065 
          S01_ARESETN
1066
1067 
            in
1068
1069 
              0
1070 
              0
1071
1072
1073
1074
1075 
          S02_ACLK
1076
1077 
            in
1078
1079
1080
1081 
          S02_ARESETN
1082
1083 
            in
1084
1085 
              0
1086 
              0
1087
1088
1089
1090
1091 
          M05_ACLK
1092
1093 
            in
1094
1095
1096
1097 
          M05_ARESETN
1098
1099 
            in
1100
1101 
              0
1102 
              0
1103
1104
1105
1106
1107
1108
1109 
 
1110
1111 
    xilinx.com
1112 
    BlockDiagram/base_microblaze_design_imp
1113 
    microblaze_0_axi_periph_imp
1114 
    1.00.a
1115
1116
1117 
        xbar
1118
1119
1120 
          base_microblaze_design_xbar_0
1121 
          3
1122 
          6
1123 
          0
1124
1125
1126
1127 
        s00_couplers
1128
1129
1130
1131 
        s01_couplers
1132
1133
1134
1135 
        s02_couplers
1136
1137
1138
1139 
        m00_couplers
1140
1141
1142
1143 
        m01_couplers
1144
1145
1146
1147 
        m02_couplers
1148
1149
1150
1151 
        m03_couplers
1152
1153
1154
1155 
        m04_couplers
1156
1157
1158
1159 
        m05_couplers
1160
1161
1162
1163
1164
1165 
        s00_couplers_to_xbar
1166
1167
1168
1169
1170 
        s01_couplers_to_xbar
1171
1172
1173
1174
1175 
        s02_couplers_to_xbar
1176
1177
1178
1179
1180 
        xbar_to_m00_couplers
1181
1182
1183
1184
1185 
        xbar_to_m01_couplers
1186
1187
1188
1189
1190 
        xbar_to_m02_couplers
1191
1192
1193
1194
1195 
        xbar_to_m03_couplers
1196
1197
1198
1199
1200 
        xbar_to_m04_couplers
1201
1202
1203
1204
1205 
        xbar_to_m05_couplers
1206
1207
1208
1209
1210
1211
1212 
        microblaze_0_axi_periph_ACLK_net
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226 
        microblaze_0_axi_periph_ARESETN_net
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240 
        S00_ACLK_1
1241
1242
1243
1244
1245 
        S00_ARESETN_1
1246
1247
1248
1249
1250 
        S01_ACLK_1
1251
1252
1253
1254
1255 
        S01_ARESETN_1
1256
1257
1258
1259
1260 
        S02_ACLK_1
1261
1262
1263
1264
1265 
        S02_ARESETN_1
1266
1267
1268
1269
1270 
        M00_ACLK_1
1271
1272
1273
1274
1275 
        M00_ARESETN_1
1276
1277
1278
1279
1280 
        M01_ACLK_1
1281
1282
1283
1284
1285 
        M01_ARESETN_1
1286
1287
1288
1289
1290 
        M02_ACLK_1
1291
1292
1293
1294
1295 
        M02_ARESETN_1
1296
1297
1298
1299
1300 
        M03_ACLK_1
1301
1302
1303
1304
1305 
        M03_ARESETN_1
1306
1307
1308
1309
1310 
        M04_ACLK_1
1311
1312
1313
1314
1315 
        M04_ARESETN_1
1316
1317
1318
1319
1320 
        M05_ACLK_1
1321
1322
1323
1324
1325 
        M05_ARESETN_1
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360 
 
1361
1362 
    xilinx.com
1363 
    BlockDiagram/base_microblaze_design_imp/microblaze_0_axi_periph_imp
1364 
    m05_couplers
1365 
    1.00.a
1366
1367
1368 
        M_AXI
1369
1370
1371
1372
1373
1374 
        S_AXI
1375
1376
1377
1378
1379
1380 
        CLK.M_ACLK
1381 
        Clk
1382 
        Clock
1383
1384
1385
1386
1387
1388
1389 
              CLK
1390
1391
1392 
              M_ACLK
1393
1394
1395
1396
1397
1398 
            ASSOCIATED_BUSIF
1399 
            M_AXI
1400
1401
1402 
            ASSOCIATED_RESET
1403 
            M_ARESETN
1404
1405
1406
1407
1408 
        RST.M_ARESETN
1409 
        Reset
1410 
        Reset
1411
1412
1413
1414
1415
1416
1417 
              RST
1418
1419
1420 
              M_ARESETN
1421
1422
1423
1424
1425
1426 
        CLK.S_ACLK
1427 
        Clk
1428 
        Clock
1429
1430
1431
1432
1433
1434
1435 
              CLK
1436
1437
1438 
              S_ACLK
1439
1440
1441
1442
1443
1444 
            ASSOCIATED_BUSIF
1445 
            S_AXI
1446
1447
1448 
            ASSOCIATED_RESET
1449 
            S_ARESETN
1450
1451
1452
1453
1454 
        RST.S_ARESETN
1455 
        Reset
1456 
        Reset
1457
1458
1459
1460
1461
1462
1463 
              RST
1464
1465
1466 
              S_ARESETN
1467
1468
1469
1470
1471
1472
1473
1474
1475 
          BlockDiagram
1476 
          :vivado.xilinx.com:
1477
1478
1479
1480
1481
1482 
          M_ACLK
1483
1484 
            in
1485
1486
1487
1488 
          M_ARESETN
1489
1490 
            in
1491
1492 
              0
1493 
              0
1494
1495
1496
1497
1498 
          S_ACLK
1499
1500 
            in
1501
1502
1503
1504 
          S_ARESETN
1505
1506 
            in
1507
1508 
              0
1509 
              0
1510
1511
1512
1513
1514
1515
1516 
 
1517
1518 
    xilinx.com
1519 
    BlockDiagram/base_microblaze_design_imp/microblaze_0_axi_periph_imp
1520 
    m05_couplers_imp
1521 
    1.00.a
1522
1523
1524 
        auto_pc
1525
1526
1527 
          base_microblaze_design_auto_pc_4
1528 
          AXI4
1529 
          AXI4LITE
1530
1531
1532
1533
1534
1535
1536 
        S_ACLK_1
1537
1538
1539
1540
1541 
        S_ARESETN_1
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555 
 
1556
1557 
    xilinx.com
1558 
    BlockDiagram/base_microblaze_design_imp/microblaze_0_axi_periph_imp
1559 
    m04_couplers
1560 
    1.00.a
1561
1562
1563 
        M_AXI
1564
1565
1566
1567
1568
1569 
        S_AXI
1570
1571
1572
1573
1574
1575 
        CLK.M_ACLK
1576 
        Clk
1577 
        Clock
1578
1579
1580
1581
1582
1583
1584 
              CLK
1585
1586
1587 
              M_ACLK
1588
1589
1590
1591
1592
1593 
            ASSOCIATED_BUSIF
1594 
            M_AXI
1595
1596
1597 
            ASSOCIATED_RESET
1598 
            M_ARESETN
1599
1600
1601
1602
1603 
        RST.M_ARESETN
1604 
        Reset
1605 
        Reset
1606
1607
1608
1609
1610
1611
1612 
              RST
1613
1614
1615 
              M_ARESETN
1616
1617
1618
1619
1620
1621 
        CLK.S_ACLK
1622 
        Clk
1623 
        Clock
1624
1625
1626
1627
1628
1629
1630 
              CLK
1631
1632
1633 
              S_ACLK
1634
1635
1636
1637
1638
1639 
            ASSOCIATED_BUSIF
1640 
            S_AXI
1641
1642
1643 
            ASSOCIATED_RESET
1644 
            S_ARESETN
1645
1646
1647
1648
1649 
        RST.S_ARESETN
1650 
        Reset
1651 
        Reset
1652
1653
1654
1655
1656
1657
1658 
              RST
1659
1660
1661 
              S_ARESETN
1662
1663
1664
1665
1666
1667
1668
1669
1670 
          BlockDiagram
1671 
          :vivado.xilinx.com:
1672
1673
1674
1675
1676
1677 
          M_ACLK
1678
1679 
            in
1680
1681
1682
1683 
          M_ARESETN
1684
1685 
            in
1686
1687 
              0
1688 
              0
1689
1690
1691
1692
1693 
          S_ACLK
1694
1695 
            in
1696
1697
1698
1699 
          S_ARESETN
1700
1701 
            in
1702
1703 
              0
1704 
              0
1705
1706
1707
1708
1709
1710
1711 
 
1712
1713 
    xilinx.com
1714 
    BlockDiagram/base_microblaze_design_imp/microblaze_0_axi_periph_imp
1715 
    m04_couplers_imp
1716 
    1.00.a
1717
1718
1719
1720
1721
1722
1723
1724
1725 
 
1726
1727 
    xilinx.com
1728 
    BlockDiagram/base_microblaze_design_imp/microblaze_0_axi_periph_imp
1729 
    m03_couplers
1730 
    1.00.a
1731
1732
1733 
        M_AXI
1734
1735
1736
1737
1738
1739 
        S_AXI
1740
1741
1742
1743
1744
1745 
        CLK.M_ACLK
1746 
        Clk
1747 
        Clock
1748
1749
1750
1751
1752
1753
1754 
              CLK
1755
1756
1757 
              M_ACLK
1758
1759
1760
1761
1762
1763 
            ASSOCIATED_BUSIF
1764 
            M_AXI
1765
1766
1767 
            ASSOCIATED_RESET
1768 
            M_ARESETN
1769
1770
1771
1772
1773 
        RST.M_ARESETN
1774 
        Reset
1775 
        Reset
1776
1777
1778
1779
1780
1781
1782 
              RST
1783
1784
1785 
              M_ARESETN
1786
1787
1788
1789
1790
1791 
        CLK.S_ACLK
1792 
        Clk
1793 
        Clock
1794
1795
1796
1797
1798
1799
1800 
              CLK
1801
1802
1803 
              S_ACLK
1804
1805
1806
1807
1808
1809 
            ASSOCIATED_BUSIF
1810 
            S_AXI
1811
1812
1813 
            ASSOCIATED_RESET
1814 
            S_ARESETN
1815
1816
1817
1818
1819 
        RST.S_ARESETN
1820 
        Reset
1821 
        Reset
1822
1823
1824
1825
1826
1827
1828 
              RST
1829
1830
1831 
              S_ARESETN
1832
1833
1834
1835
1836
1837
1838
1839
1840 
          BlockDiagram
1841 
          :vivado.xilinx.com:
1842
1843
1844
1845
1846
1847 
          M_ACLK
1848
1849 
            in
1850
1851
1852
1853 
          M_ARESETN
1854
1855 
            in
1856
1857 
              0
1858 
              0
1859
1860
1861
1862
1863 
          S_ACLK
1864
1865 
            in
1866
1867
1868
1869 
          S_ARESETN
1870
1871 
            in
1872
1873 
              0
1874 
              0
1875
1876
1877
1878
1879
1880
1881 
 
1882
1883 
    xilinx.com
1884 
    BlockDiagram/base_microblaze_design_imp/microblaze_0_axi_periph_imp
1885 
    m03_couplers_imp
1886 
    1.00.a
1887
1888
1889 
        auto_pc
1890
1891
1892 
          base_microblaze_design_auto_pc_3
1893 
          AXI4
1894 
          AXI4LITE
1895
1896
1897
1898
1899
1900
1901 
        S_ACLK_1
1902
1903
1904
1905
1906 
        S_ARESETN_1
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920 
 
1921
1922 
    xilinx.com
1923 
    BlockDiagram/base_microblaze_design_imp/microblaze_0_axi_periph_imp
1924 
    m02_couplers
1925 
    1.00.a
1926
1927
1928 
        M_AXI
1929
1930
1931
1932
1933
1934 
        S_AXI
1935
1936
1937
1938
1939
1940 
        CLK.M_ACLK
1941 
        Clk
1942 
        Clock
1943
1944
1945
1946
1947
1948
1949 
              CLK
1950
1951
1952 
              M_ACLK
1953
1954
1955
1956
1957
1958 
            ASSOCIATED_BUSIF
1959 
            M_AXI
1960
1961
1962 
            ASSOCIATED_RESET
1963 
            M_ARESETN
1964
1965
1966
1967
1968 
        RST.M_ARESETN
1969 
        Reset
1970 
        Reset
1971
1972
1973
1974
1975
1976
1977 
              RST
1978
1979
1980 
              M_ARESETN
1981
1982
1983
1984
1985
1986 
        CLK.S_ACLK
1987 
        Clk
1988 
        Clock
1989
1990
1991
1992
1993
1994
1995 
              CLK
1996
1997
1998 
              S_ACLK
1999
2000
2001
2002
2003
2004 
            ASSOCIATED_BUSIF
2005 
            S_AXI
2006
2007
2008 
            ASSOCIATED_RESET
2009 
            S_ARESETN
2010
2011
2012
2013
2014 
        RST.S_ARESETN
2015 
        Reset
2016 
        Reset
2017
2018
2019
2020
2021
2022
2023 
              RST
2024
2025
2026 
              S_ARESETN
2027
2028
2029
2030
2031
2032
2033
2034
2035 
          BlockDiagram
2036 
          :vivado.xilinx.com:
2037
2038
2039
2040
2041
2042 
          M_ACLK
2043
2044 
            in
2045
2046
2047
2048 
          M_ARESETN
2049
2050 
            in
2051
2052 
              0
2053 
              0
2054
2055
2056
2057
2058 
          S_ACLK
2059
2060 
            in
2061
2062
2063
2064 
          S_ARESETN
2065
2066 
            in
2067
2068 
              0
2069 
              0
2070
2071
2072
2073
2074
2075
2076 
 
2077
2078 
    xilinx.com
2079 
    BlockDiagram/base_microblaze_design_imp/microblaze_0_axi_periph_imp
2080 
    m02_couplers_imp
2081 
    1.00.a
2082
2083
2084 
        auto_pc
2085
2086
2087 
          base_microblaze_design_auto_pc_2
2088 
          AXI4
2089 
          AXI4LITE
2090
2091
2092
2093
2094
2095
2096 
        S_ACLK_1
2097
2098
2099
2100
2101 
        S_ARESETN_1
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115 
 
2116
2117 
    xilinx.com
2118 
    BlockDiagram/base_microblaze_design_imp/microblaze_0_axi_periph_imp
2119 
    m01_couplers
2120 
    1.00.a
2121
2122
2123 
        M_AXI
2124
2125
2126
2127
2128
2129 
        S_AXI
2130
2131
2132
2133
2134
2135 
        CLK.M_ACLK
2136 
        Clk
2137 
        Clock
2138
2139
2140
2141
2142
2143
2144 
              CLK
2145
2146
2147 
              M_ACLK
2148
2149
2150
2151
2152
2153 
            ASSOCIATED_BUSIF
2154 
            M_AXI
2155
2156
2157 
            ASSOCIATED_RESET
2158 
            M_ARESETN
2159
2160
2161
2162
2163 
        RST.M_ARESETN
2164 
        Reset
2165 
        Reset
2166
2167
2168
2169
2170
2171
2172 
              RST
2173
2174
2175 
              M_ARESETN
2176
2177
2178
2179
2180
2181 
        CLK.S_ACLK
2182 
        Clk
2183 
        Clock
2184
2185
2186
2187
2188
2189
2190 
              CLK
2191
2192
2193 
              S_ACLK
2194
2195
2196
2197
2198
2199 
            ASSOCIATED_BUSIF
2200 
            S_AXI
2201
2202
2203 
            ASSOCIATED_RESET
2204 
            S_ARESETN
2205
2206
2207
2208
2209 
        RST.S_ARESETN
2210 
        Reset
2211 
        Reset
2212
2213
2214
2215
2216
2217
2218 
              RST
2219
2220
2221 
              S_ARESETN
2222
2223
2224
2225
2226
2227
2228
2229
2230 
          BlockDiagram
2231 
          :vivado.xilinx.com:
2232
2233
2234
2235
2236
2237 
          M_ACLK
2238
2239 
            in
2240
2241
2242
2243 
          M_ARESETN
2244
2245 
            in
2246
2247 
              0
2248 
              0
2249
2250
2251
2252
2253 
          S_ACLK
2254
2255 
            in
2256
2257
2258
2259 
          S_ARESETN
2260
2261 
            in
2262
2263 
              0
2264 
              0
2265
2266
2267
2268
2269
2270
2271 
 
2272
2273 
    xilinx.com
2274 
    BlockDiagram/base_microblaze_design_imp/microblaze_0_axi_periph_imp
2275 
    m01_couplers_imp
2276 
    1.00.a
2277
2278
2279 
        auto_pc
2280
2281
2282 
          base_microblaze_design_auto_pc_1
2283 
          AXI4
2284 
          AXI4LITE
2285
2286
2287
2288
2289
2290
2291 
        S_ACLK_1
2292
2293
2294
2295
2296 
        S_ARESETN_1
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310 
 
2311
2312 
    xilinx.com
2313 
    BlockDiagram/base_microblaze_design_imp/microblaze_0_axi_periph_imp
2314 
    m00_couplers
2315 
    1.00.a
2316
2317
2318 
        M_AXI
2319
2320
2321
2322
2323
2324 
        S_AXI
2325
2326
2327
2328
2329
2330 
        CLK.M_ACLK
2331 
        Clk
2332 
        Clock
2333
2334
2335
2336
2337
2338
2339 
              CLK
2340
2341
2342 
              M_ACLK
2343
2344
2345
2346
2347
2348 
            ASSOCIATED_BUSIF
2349 
            M_AXI
2350
2351
2352 
            ASSOCIATED_RESET
2353 
            M_ARESETN
2354
2355
2356
2357
2358 
        RST.M_ARESETN
2359 
        Reset
2360 
        Reset
2361
2362
2363
2364
2365
2366
2367 
              RST
2368
2369
2370 
              M_ARESETN
2371
2372
2373
2374
2375
2376 
        CLK.S_ACLK
2377 
        Clk
2378 
        Clock
2379
2380
2381
2382
2383
2384
2385 
              CLK
2386
2387
2388 
              S_ACLK
2389
2390
2391
2392
2393
2394 
            ASSOCIATED_BUSIF
2395 
            S_AXI
2396
2397
2398 
            ASSOCIATED_RESET
2399 
            S_ARESETN
2400
2401
2402
2403
2404 
        RST.S_ARESETN
2405 
        Reset
2406 
        Reset
2407
2408
2409
2410
2411
2412
2413 
              RST
2414
2415
2416 
              S_ARESETN
2417
2418
2419
2420
2421
2422
2423
2424
2425 
          BlockDiagram
2426 
          :vivado.xilinx.com:
2427
2428
2429
2430
2431
2432 
          M_ACLK
2433
2434 
            in
2435
2436
2437
2438 
          M_ARESETN
2439
2440 
            in
2441
2442 
              0
2443 
              0
2444
2445
2446
2447
2448 
          S_ACLK
2449
2450 
            in
2451
2452
2453
2454 
          S_ARESETN
2455
2456 
            in
2457
2458 
              0
2459 
              0
2460
2461
2462
2463
2464
2465
2466 
 
2467
2468 
    xilinx.com
2469 
    BlockDiagram/base_microblaze_design_imp/microblaze_0_axi_periph_imp
2470 
    m00_couplers_imp
2471 
    1.00.a
2472
2473
2474 
        auto_pc
2475
2476
2477 
          base_microblaze_design_auto_pc_0
2478 
          AXI4
2479 
          AXI4LITE
2480
2481
2482
2483
2484
2485
2486 
        S_ACLK_1
2487
2488
2489
2490
2491 
        S_ARESETN_1
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505 
 
2506
2507 
    xilinx.com
2508 
    BlockDiagram/base_microblaze_design_imp/microblaze_0_axi_periph_imp
2509 
    s02_couplers
2510 
    1.00.a
2511
2512
2513 
        M_AXI
2514
2515
2516
2517
2518
2519 
        S_AXI
2520
2521
2522
2523
2524
2525 
        CLK.M_ACLK
2526 
        Clk
2527 
        Clock
2528
2529
2530
2531
2532
2533
2534 
              CLK
2535
2536
2537 
              M_ACLK
2538
2539
2540
2541
2542
2543 
            ASSOCIATED_BUSIF
2544 
            M_AXI
2545
2546
2547 
            ASSOCIATED_RESET
2548 
            M_ARESETN
2549
2550
2551
2552
2553 
        RST.M_ARESETN
2554 
        Reset
2555 
        Reset
2556
2557
2558
2559
2560
2561
2562 
              RST
2563
2564
2565 
              M_ARESETN
2566
2567
2568
2569
2570
2571 
        CLK.S_ACLK
2572 
        Clk
2573 
        Clock
2574
2575
2576
2577
2578
2579
2580 
              CLK
2581
2582
2583 
              S_ACLK
2584
2585
2586
2587
2588
2589 
            ASSOCIATED_BUSIF
2590 
            S_AXI
2591
2592
2593 
            ASSOCIATED_RESET
2594 
            S_ARESETN
2595
2596
2597
2598
2599 
        RST.S_ARESETN
2600 
        Reset
2601 
        Reset
2602
2603
2604
2605
2606
2607
2608 
              RST
2609
2610
2611 
              S_ARESETN
2612
2613
2614
2615
2616
2617
2618
2619
2620 
          BlockDiagram
2621 
          :vivado.xilinx.com:
2622
2623
2624
2625
2626
2627 
          M_ACLK
2628
2629 
            in
2630
2631
2632
2633 
          M_ARESETN
2634
2635 
            in
2636
2637 
              0
2638 
              0
2639
2640
2641
2642
2643 
          S_ACLK
2644
2645 
            in
2646
2647
2648
2649 
          S_ARESETN
2650
2651 
            in
2652
2653 
              0
2654 
              0
2655
2656
2657
2658
2659
2660
2661 
 
2662
2663 
    xilinx.com
2664 
    BlockDiagram/base_microblaze_design_imp/microblaze_0_axi_periph_imp
2665 
    s02_couplers_imp
2666 
    1.00.a
2667
2668
2669
2670
2671
2672
2673
2674
2675 
 
2676
2677 
    xilinx.com
2678 
    BlockDiagram/base_microblaze_design_imp/microblaze_0_axi_periph_imp
2679 
    s01_couplers
2680 
    1.00.a
2681
2682
2683 
        M_AXI
2684
2685
2686
2687
2688
2689 
        S_AXI
2690
2691
2692
2693
2694
2695 
        CLK.M_ACLK
2696 
        Clk
2697 
        Clock
2698
2699
2700
2701
2702
2703
2704 
              CLK
2705
2706
2707 
              M_ACLK
2708
2709
2710
2711
2712
2713 
            ASSOCIATED_BUSIF
2714 
            M_AXI
2715
2716
2717 
            ASSOCIATED_RESET
2718 
            M_ARESETN
2719
2720
2721
2722
2723 
        RST.M_ARESETN
2724 
        Reset
2725 
        Reset
2726
2727
2728
2729
2730
2731
2732 
              RST
2733
2734
2735 
              M_ARESETN
2736
2737
2738
2739
2740
2741 
        CLK.S_ACLK
2742 
        Clk
2743 
        Clock
2744
2745
2746
2747
2748
2749
2750 
              CLK
2751
2752
2753 
              S_ACLK
2754
2755
2756
2757
2758
2759 
            ASSOCIATED_BUSIF
2760 
            S_AXI
2761
2762
2763 
            ASSOCIATED_RESET
2764 
            S_ARESETN
2765
2766
2767
2768
2769 
        RST.S_ARESETN
2770 
        Reset
2771 
        Reset
2772
2773
2774
2775
2776
2777
2778 
              RST
2779
2780
2781 
              S_ARESETN
2782
2783
2784
2785
2786
2787
2788
2789
2790 
          BlockDiagram
2791 
          :vivado.xilinx.com:
2792
2793
2794
2795
2796
2797 
          M_ACLK
2798
2799 
            in
2800
2801
2802
2803 
          M_ARESETN
2804
2805 
            in
2806
2807 
              0
2808 
              0
2809
2810
2811
2812
2813 
          S_ACLK
2814
2815 
            in
2816
2817
2818
2819 
          S_ARESETN
2820
2821 
            in
2822
2823 
              0
2824 
              0
2825
2826
2827
2828
2829
2830
2831 
 
2832
2833 
    xilinx.com
2834 
    BlockDiagram/base_microblaze_design_imp/microblaze_0_axi_periph_imp
2835 
    s01_couplers_imp
2836 
    1.00.a
2837
2838
2839
2840
2841
2842
2843
2844
2845 
 
2846
2847 
    xilinx.com
2848 
    BlockDiagram/base_microblaze_design_imp/microblaze_0_axi_periph_imp
2849 
    s00_couplers
2850 
    1.00.a
2851
2852
2853 
        M_AXI
2854
2855
2856
2857
2858
2859 
        S_AXI
2860
2861
2862
2863
2864
2865 
        CLK.M_ACLK
2866 
        Clk
2867 
        Clock
2868
2869
2870
2871
2872
2873
2874 
              CLK
2875
2876
2877 
              M_ACLK
2878
2879
2880
2881
2882
2883 
            ASSOCIATED_BUSIF
2884 
            M_AXI
2885
2886
2887 
            ASSOCIATED_RESET
2888 
            M_ARESETN
2889
2890
2891
2892
2893 
        RST.M_ARESETN
2894 
        Reset
2895 
        Reset
2896
2897
2898
2899
2900
2901
2902 
              RST
2903
2904
2905 
              M_ARESETN
2906
2907
2908
2909
2910
2911 
        CLK.S_ACLK
2912 
        Clk
2913 
        Clock
2914
2915
2916
2917
2918
2919
2920 
              CLK
2921
2922
2923 
              S_ACLK
2924
2925
2926
2927
2928
2929 
            ASSOCIATED_BUSIF
2930 
            S_AXI
2931
2932
2933 
            ASSOCIATED_RESET
2934 
            S_ARESETN
2935
2936
2937
2938
2939 
        RST.S_ARESETN
2940 
        Reset
2941 
        Reset
2942
2943
2944
2945
2946
2947
2948 
              RST
2949
2950
2951 
              S_ARESETN
2952
2953
2954
2955
2956
2957
2958
2959
2960 
          BlockDiagram
2961 
          :vivado.xilinx.com:
2962
2963
2964
2965
2966
2967 
          M_ACLK
2968
2969 
            in
2970
2971
2972
2973 
          M_ARESETN
2974
2975 
            in
2976
2977 
              0
2978 
              0
2979
2980
2981
2982
2983 
          S_ACLK
2984
2985 
            in
2986
2987
2988
2989 
          S_ARESETN
2990
2991 
            in
2992
2993 
              0
2994 
              0
2995
2996
2997
2998
2999
3000
3001 
 
3002
3003 
    xilinx.com
3004 
    BlockDiagram/base_microblaze_design_imp/microblaze_0_axi_periph_imp
3005 
    s00_couplers_imp
3006 
    1.00.a
3007
3008
3009 
        auto_pc
3010
3011
3012 
          base_microblaze_design_auto_pc_5
3013 
          AXI4LITE
3014 
          AXI4
3015
3016
3017
3018
3019
3020
3021 
        S_ACLK_1
3022
3023
3024
3025
3026 
        S_ARESETN_1
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040 
 
3041
3042 
    xilinx.com
3043 
    BlockDiagram/base_microblaze_design_imp
3044 
    microblaze_0_local_memory
3045 
    1.00.a
3046
3047
3048 
        DLMB
3049
3050
3051
3052
3053
3054 
        ILMB
3055
3056
3057
3058
3059
3060 
        CLK.LMB_CLK
3061 
        Clk
3062 
        Clock
3063
3064
3065
3066
3067
3068
3069 
              CLK
3070
3071
3072 
              LMB_Clk
3073
3074
3075
3076
3077
3078 
        RST.SYS_RST
3079 
        Reset
3080 
        Reset
3081
3082
3083
3084
3085
3086
3087 
              RST
3088
3089
3090 
              SYS_Rst
3091
3092
3093
3094
3095
3096
3097
3098
3099 
          BlockDiagram
3100 
          :vivado.xilinx.com:
3101
3102
3103
3104
3105
3106 
          LMB_Clk
3107
3108 
            in
3109
3110
3111
3112 
          SYS_Rst
3113
3114 
            in
3115
3116 
              0
3117 
              0
3118
3119
3120
3121
3122
3123
3124 
 
3125
3126 
    xilinx.com
3127 
    BlockDiagram/base_microblaze_design_imp
3128 
    microblaze_0_local_memory_imp
3129 
    1.00.a
3130
3131
3132 
        dlmb_v10
3133
3134
3135 
          base_microblaze_design_dlmb_v10_0
3136
3137
3138
3139 
        ilmb_v10
3140
3141
3142 
          base_microblaze_design_ilmb_v10_0
3143
3144
3145
3146 
        dlmb_bram_if_cntlr
3147
3148
3149 
          base_microblaze_design_dlmb_bram_if_cntlr_0
3150 
          0
3151
3152
3153
3154 
        ilmb_bram_if_cntlr
3155
3156
3157 
          base_microblaze_design_ilmb_bram_if_cntlr_0
3158 
          0
3159
3160
3161
3162 
        lmb_bram
3163
3164
3165 
          base_microblaze_design_lmb_bram_0
3166 
          True_Dual_Port_RAM
3167 
          BRAM_Controller
3168
3169
3170
3171
3172
3173 
        microblaze_0_dlmb_bus
3174
3175
3176
3177
3178 
        microblaze_0_ilmb_bus
3179
3180
3181
3182
3183 
        microblaze_0_dlmb_cntlr
3184
3185
3186
3187
3188 
        microblaze_0_ilmb_cntlr
3189
3190
3191
3192
3193
3194
3195 
        microblaze_0_Clk
3196
3197
3198
3199
3200
3201
3202
3203 
        SYS_Rst_1
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220 
 
3221
3222 
    xilinx.com
3223 
    Addressing/microblaze_0
3224 
    microblaze
3225 
    9.5
3226
3227
3228 
        Data
3229 
        4G
3230 
        32
3231
3232
3233 
            SEG_dlmb_bram_if_cntlr_Mem
3234 
            /microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem
3235 
            0x00000000
3236 
            128K
3237
3238
3239 
            SEG_axi_gpio_0_Reg
3240 
            /axi_gpio_0/S_AXI/Reg
3241 
            0x40000000
3242 
            64K
3243
3244
3245 
            SEG_axi_uartlite_0_Reg
3246 
            /axi_uartlite_0/S_AXI/Reg
3247 
            0x40600000
3248 
            64K
3249
3250
3251 
            SEG_tri_mode_emac_0_reg0
3252 
            /tri_mode_emac_0/s_axi/reg0
3253 
            0x44A00000
3254 
            64K
3255
3256
3257 
            SEG_axi_dma_0_Reg
3258 
            /axi_dma_0/S_AXI_LITE/Reg
3259 
            0x41E00000
3260 
            64K
3261
3262
3263 
            SEG_axi_bram_ctrl_0_Mem0
3264 
            /axi_bram_ctrl_0/S_AXI/Mem0
3265 
            0xC0000000
3266 
            8K
3267
3268
3269 
            SEG_axi_intc_0_Reg
3270 
            /axi_intc_0/s_axi/Reg
3271 
            0x41200000
3272 
            64K
3273
3274
3275
3276
3277 
        Instruction
3278 
        4G
3279 
        32
3280
3281
3282 
            SEG_ilmb_bram_if_cntlr_Mem
3283 
            /microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem
3284 
            0x00000000
3285 
            128K
3286
3287
3288
3289
3290
3291 
 
3292
3293 
    xilinx.com
3294 
    Addressing/mdm_1
3295 
    mdm
3296 
    3.2
3297
3298
3299 
 
3300
3301 
    xilinx.com
3302 
    Addressing/axi_dma_0
3303 
    axi_dma
3304 
    7.1
3305
3306
3307 
        Data_MM2S
3308 
        4G
3309 
        32
3310
3311
3312 
            SEG_axi_bram_ctrl_0_Mem0
3313 
            /axi_bram_ctrl_0/S_AXI/Mem0
3314 
            0xC0000000
3315 
            8K
3316
3317
3318 
            SEG_axi_dma_0_Reg
3319 
            /axi_dma_0/S_AXI_LITE/Reg
3320 
            0x41E00000
3321 
            64K
3322
3323
3324 
            SEG_axi_gpio_0_Reg
3325 
            /axi_gpio_0/S_AXI/Reg
3326 
            0x40000000
3327 
            64K
3328
3329
3330 
            SEG_axi_uartlite_0_Reg
3331 
            /axi_uartlite_0/S_AXI/Reg
3332 
            0x40600000
3333 
            64K
3334
3335
3336 
            SEG_tri_mode_emac_0_reg0
3337 
            /tri_mode_emac_0/s_axi/reg0
3338 
            0x44A00000
3339 
            64K
3340
3341
3342 
            SEG_axi_intc_0_Reg
3343 
            /axi_intc_0/s_axi/Reg
3344 
            0x41200000
3345 
            64K
3346
3347
3348
3349
3350 
        Data_S2MM
3351 
        4G
3352 
        32
3353
3354
3355 
            SEG_axi_bram_ctrl_0_Mem0
3356 
            /axi_bram_ctrl_0/S_AXI/Mem0
3357 
            0xC0000000
3358 
            8K
3359
3360
3361 
            SEG_axi_dma_0_Reg
3362 
            /axi_dma_0/S_AXI_LITE/Reg
3363 
            0x41E00000
3364 
            64K
3365
3366
3367 
            SEG_axi_gpio_0_Reg
3368 
            /axi_gpio_0/S_AXI/Reg
3369 
            0x40000000
3370 
            64K
3371
3372
3373 
            SEG_axi_uartlite_0_Reg
3374 
            /axi_uartlite_0/S_AXI/Reg
3375 
            0x40600000
3376 
            64K
3377
3378
3379 
            SEG_tri_mode_emac_0_reg0
3380 
            /tri_mode_emac_0/s_axi/reg0
3381 
            0x44A00000
3382 
            64K
3383
3384
3385 
            SEG_axi_intc_0_Reg
3386 
            /axi_intc_0/s_axi/Reg
3387 
            0x41200000
3388 
            64K
3389
3390
3391
3392
3393
3394 
 
3395

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