Subversion Repositories 1g_ethernet_dpi

#set_property mark_debug true [get_nets [list {u0/microblaze_0/M_AXI_DP_ARADDR[4]} {u0/microblaze_0/M_AXI_DP_ARADDR[20]} {u0/microblaze_0/M_AXI_DP_AWADDR[2]} {u0/microblaze_0/M_AXI_DP_AWADDR[18]} {u0/microblaze_0/M_AXI_DP_AWPROT[2]} {u0/microblaze_0/M_AXI_DP_RDATA[13]} {u0/microblaze_0/M_AXI_DP_RDATA[29]} {u0/microblaze_0/M_AXI_DP_WDATA[10]} {u0/microblaze_0/M_AXI_DP_AWADDR[15]} {u0/microblaze_0/M_AXI_DP_ARADDR[1]} {u0/microblaze_0/M_AXI_DP_ARADDR[17]} {u0/microblaze_0/M_AXI_DP_ARPROT[2]} {u0/microblaze_0/M_AXI_DP_AWADDR[31]} {u0/microblaze_0/M_AXI_DP_RDATA[9]} {u0/microblaze_0/M_AXI_DP_RDATA[26]} {u0/microblaze_0/M_AXI_DP_WDATA[8]} {u0/microblaze_0/M_AXI_DP_WDATA[24]} {u0/microblaze_0/M_AXI_DP_AWADDR[24]} {u0/microblaze_0/M_AXI_DP_ARADDR[26]} {u0/microblaze_0/M_AXI_DP_ARADDR[9]} {u0/microblaze_0/M_AXI_DP_AWADDR[8]} {u0/microblaze_0/M_AXI_DP_RDATA[3]} {u0/microblaze_0/M_AXI_DP_RDATA[19]} {u0/microblaze_0/M_AXI_DP_WDATA[1]} {u0/microblaze_0/M_AXI_DP_WDATA[17]} {u0/microblaze_0/M_AXI_DP_WDATA[29]} {u0/microblaze_0/M_AXI_DP_AWADDR[21]} {u0/microblaze_0/M_AXI_DP_AWADDR[5]} {u0/microblaze_0/M_AXI_DP_ARADDR[7]} {u0/microblaze_0/M_AXI_DP_ARADDR[23]} {u0/microblaze_0/M_AXI_DP_RDATA[0]} {u0/microblaze_0/M_AXI_DP_RDATA[16]} {u0/microblaze_0/M_AXI_DP_RRESP[0]} {u0/microblaze_0/M_AXI_DP_WDATA[14]} {u0/microblaze_0/M_AXI_DP_WDATA[26]} {u0/microblaze_0/M_AXI_DP_AWADDR[14]} {u0/microblaze_0/M_AXI_DP_ARADDR[0]} {u0/microblaze_0/M_AXI_DP_WSTRB[3]} {u0/microblaze_0/M_AXI_DP_ARADDR[16]} {u0/microblaze_0/M_AXI_DP_ARPROT[1]} {u0/microblaze_0/M_AXI_DP_AWADDR[30]} {u0/microblaze_0/M_AXI_DP_RDATA[11]} {u0/microblaze_0/M_AXI_DP_RDATA[25]} {u0/microblaze_0/M_AXI_DP_WDATA[7]} {u0/microblaze_0/M_AXI_DP_WDATA[23]} {u0/microblaze_0/M_AXI_DP_AWADDR[27]} {u0/microblaze_0/M_AXI_DP_ARADDR[29]} {u0/microblaze_0/M_AXI_DP_ARADDR[13]} {u0/microblaze_0/M_AXI_DP_AWADDR[10]} {u0/microblaze_0/M_AXI_DP_RDATA[6]} {u0/microblaze_0/M_AXI_DP_RDATA[22]} {u0/microblaze_0/M_AXI_DP_WDATA[4]} {u0/microblaze_0/M_AXI_DP_WDATA[20]} {u0/microblaze_0/M_AXI_DP_WSTRB[0]} {u0/microblaze_0/M_AXI_DP_AWADDR[20]} {u0/microblaze_0/M_AXI_DP_ARADDR[6]} {u0/microblaze_0/M_AXI_DP_ARADDR[22]} {u0/microblaze_0/M_AXI_DP_AWADDR[4]} {u0/microblaze_0/M_AXI_DP_BRESP[1]} {u0/microblaze_0/M_AXI_DP_RDATA[15]} {u0/microblaze_0/M_AXI_DP_RDATA[31]} {u0/microblaze_0/M_AXI_DP_WDATA[13]} {u0/microblaze_0/M_AXI_DP_WDATA[25]} {u0/microblaze_0/M_AXI_DP_ARADDR[19]} {u0/microblaze_0/M_AXI_DP_ARADDR[3]} {u0/microblaze_0/M_AXI_DP_AWADDR[1]} {u0/microblaze_0/M_AXI_DP_AWADDR[17]} {u0/microblaze_0/M_AXI_DP_AWPROT[1]} {u0/microblaze_0/M_AXI_DP_RDATA[12]} {u0/microblaze_0/M_AXI_DP_RDATA[28]} {u0/microblaze_0/M_AXI_DP_WDATA[9]} {u0/microblaze_0/M_AXI_DP_AWADDR[26]} {u0/microblaze_0/M_AXI_DP_ARADDR[28]} {u0/microblaze_0/M_AXI_DP_ARADDR[12]} {u0/microblaze_0/M_AXI_DP_AWADDR[9]} {u0/microblaze_0/M_AXI_DP_RDATA[5]} {u0/microblaze_0/M_AXI_DP_RDATA[21]} {u0/microblaze_0/M_AXI_DP_WDATA[3]} {u0/microblaze_0/M_AXI_DP_WDATA[19]} {u0/microblaze_0/M_AXI_DP_WDATA[31]} {u0/microblaze_0/M_AXI_DP_AWADDR[23]} {u0/microblaze_0/M_AXI_DP_ARADDR[25]} {u0/microblaze_0/M_AXI_DP_ARADDR[11]} {u0/microblaze_0/M_AXI_DP_AWADDR[7]} {u0/microblaze_0/M_AXI_DP_RDATA[2]} {u0/microblaze_0/M_AXI_DP_RDATA[18]} {u0/microblaze_0/M_AXI_DP_WDATA[0]} {u0/microblaze_0/M_AXI_DP_WDATA[16]} {u0/microblaze_0/M_AXI_DP_WDATA[28]} {u0/microblaze_0/M_AXI_DP_ARADDR[18]} {u0/microblaze_0/M_AXI_DP_ARADDR[2]} {u0/microblaze_0/M_AXI_DP_AWADDR[0]} {u0/microblaze_0/M_AXI_DP_AWADDR[16]} {u0/microblaze_0/M_AXI_DP_AWPROT[0]} {u0/microblaze_0/M_AXI_DP_RDATA[10]} {u0/microblaze_0/M_AXI_DP_RDATA[27]} {u0/microblaze_0/M_AXI_DP_WDATA[11]} {u0/microblaze_0/M_AXI_DP_AWADDR[13]} {u0/microblaze_0/M_AXI_DP_ARADDR[15]} {u0/microblaze_0/M_AXI_DP_AWADDR[29]} {u0/microblaze_0/M_AXI_DP_RDATA[8]} {u0/microblaze_0/M_AXI_DP_RDATA[24]} {u0/microblaze_0/M_AXI_DP_WDATA[6]} {u0/microblaze_0/M_AXI_DP_WDATA[22]} {u0/microblaze_0/M_AXI_DP_ARADDR[31]} {u0/microblaze_0/M_AXI_DP_ARPROT[0]} {u0/microblaze_0/M_AXI_DP_WSTRB[2]} {u0/microblaze_0/M_AXI_DP_AWADDR[22]} {u0/microblaze_0/M_AXI_DP_ARADDR[24]} {u0/microblaze_0/M_AXI_DP_ARADDR[8]} {u0/microblaze_0/M_AXI_DP_AWADDR[6]} {u0/microblaze_0/M_AXI_DP_RDATA[1]} {u0/microblaze_0/M_AXI_DP_RDATA[17]} {u0/microblaze_0/M_AXI_DP_RRESP[1]} {u0/microblaze_0/M_AXI_DP_WDATA[15]} {u0/microblaze_0/M_AXI_DP_WDATA[27]} {u0/microblaze_0/M_AXI_DP_ARADDR[5]} {u0/microblaze_0/M_AXI_DP_ARADDR[21]} {u0/microblaze_0/M_AXI_DP_AWADDR[3]} {u0/microblaze_0/M_AXI_DP_AWADDR[19]} {u0/microblaze_0/M_AXI_DP_BRESP[0]} {u0/microblaze_0/M_AXI_DP_RDATA[14]} {u0/microblaze_0/M_AXI_DP_RDATA[30]} {u0/microblaze_0/M_AXI_DP_WDATA[12]} {u0/microblaze_0/M_AXI_DP_AWADDR[28]} {u0/microblaze_0/M_AXI_DP_ARADDR[30]} {u0/microblaze_0/M_AXI_DP_ARADDR[14]} {u0/microblaze_0/M_AXI_DP_AWADDR[12]} {u0/microblaze_0/M_AXI_DP_RDATA[7]} {u0/microblaze_0/M_AXI_DP_RDATA[23]} {u0/microblaze_0/M_AXI_DP_WDATA[5]} {u0/microblaze_0/M_AXI_DP_WDATA[21]} {u0/microblaze_0/M_AXI_DP_WSTRB[1]} {u0/microblaze_0/M_AXI_DP_AWADDR[25]} {u0/microblaze_0/M_AXI_DP_ARADDR[27]} {u0/microblaze_0/M_AXI_DP_ARADDR[10]} {u0/microblaze_0/M_AXI_DP_AWADDR[11]} {u0/microblaze_0/M_AXI_DP_RDATA[4]} {u0/microblaze_0/M_AXI_DP_RDATA[20]} {u0/microblaze_0/M_AXI_DP_WDATA[2]} {u0/microblaze_0/M_AXI_DP_WDATA[18]} {u0/microblaze_0/M_AXI_DP_WDATA[30]}]]

#set_property mark_debug true [get_nets [list u0/microblaze_0/M_AXI_DP_ARVALID u0/microblaze_0/M_AXI_DP_AWVALID u0/microblaze_0/M_AXI_DP_BVALID u0/microblaze_0/M_AXI_DP_RVALID u0/microblaze_0/M_AXI_DP_WVALID u0/microblaze_0/M_AXI_DP_ARREADY u0/microblaze_0/M_AXI_DP_AWREADY u0/microblaze_0/M_AXI_DP_BREADY u0/microblaze_0/M_AXI_DP_RREADY u0/microblaze_0/M_AXI_DP_WREADY]]

#set_property TRIGGER_COMPARE_VALUE eq1'h1 [get_hw_probes u0/microblaze_0/M_AXI_DP_ARVALID -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7k325t_0] -filter {CELL_NAME=~"u_ila_0"}]]

#set_property CONTROL.TRIGGER_POSITION 16 [get_hw_ilas -of_objects [get_hw_devices xc7k325t_0] -filter {CELL_NAME=~"u_ila_0"}]

#write_hw_ila_data -force mwform.zip

#display_hw_ila_data [read_hw_ila_data mwform.zip]