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URL https://opencores.org/ocsvn/1g_ethernet_dpi/1g_ethernet_dpi/trunk

Subversion Repositories 1g_ethernet_dpi

[/] [1g_ethernet_dpi/] [trunk/] [hw/] [src/] [rtl/] [tri_mode_emac/] [component.xml] - Blame information for rev 4

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Line No. Rev Author Line
1 4 kuzmi4
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  user-org
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  user
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  tri_mode_emac
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  1.0
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      s_axi
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            AWADDR
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            s_axi_awaddr
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            AWVALID
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            s_axi_awvalid
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            AWREADY
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            s_axi_awready
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            WDATA
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            s_axi_wdata
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            WVALID
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            s_axi_wvalid
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            WREADY
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            s_axi_wready
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            BRESP
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            s_axi_bresp
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            BVALID
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            s_axi_bvalid
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            BREADY
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            s_axi_bready
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            ARADDR
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            s_axi_araddr
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            ARVALID
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            s_axi_arvalid
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            ARREADY
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            s_axi_arready
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            RDATA
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            s_axi_rdata
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            RRESP
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            s_axi_rresp
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            RVALID
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            s_axi_rvalid
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            RREADY
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            s_axi_rready
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      rx_axis_fifo
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            TDATA
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            rx_axis_fifo_tdata
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            TLAST
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            rx_axis_fifo_tlast
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            TVALID
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            rx_axis_fifo_tvalid
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            TREADY
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            rx_axis_fifo_tready
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      tx_axis_fifo
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            TDATA
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            tx_axis_fifo_tdata
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            TLAST
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            tx_axis_fifo_tlast
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            TVALID
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            tx_axis_fifo_tvalid
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            TREADY
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            tx_axis_fifo_tready
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      s_axi_resetn
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            RST
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            s_axi_resetn
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          POLARITY
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          ACTIVE_LOW
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      s_axi_aclk
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            CLK
257
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            s_axi_aclk
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          ASSOCIATED_BUSIF
266 
          s_axi
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          ASSOCIATED_RESET
270 
          s_axi_resetn
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      rx_axi_rstn
276
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            RST
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            rx_axi_rstn
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          POLARITY
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          ACTIVE_LOW
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      rx_fifo_resetn
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            RST
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            rx_fifo_resetn
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          POLARITY
314 
          ACTIVE_LOW
315
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      tx_axi_rstn
320
321
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324
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            RST
327
328
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            tx_axi_rstn
330
331
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          POLARITY
336 
          ACTIVE_LOW
337
338
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      tx_fifo_resetn
342
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            RST
349
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            tx_fifo_resetn
352
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          POLARITY
358 
          ACTIVE_LOW
359
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      rx_fifo_clock
364
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            CLK
371
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373 
            rx_fifo_clock
374
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376
377
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          ASSOCIATED_RESET
380 
          rx_fifo_resetn:rx_axi_rstn
381
382
383 
          ASSOCIATED_BUSIF
384 
          rx_axis_fifo
385
386
387
388
389 
      tx_fifo_clock
390
391
392
393
394
395
396 
            CLK
397
398
399 
            tx_fifo_clock
400
401
402
403
404
405 
          ASSOCIATED_RESET
406 
          tx_fifo_resetn:tx_axi_rstn
407
408
409 
          ASSOCIATED_BUSIF
410 
          tx_axis_fifo
411
412
413
414
415 
      tmemac_1
416
417
418
419
420
421
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            gtx_clk
423
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425 
            gtx_clk
426
427
428
429
430 
            glbl_rstn
431
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433 
            glbl_rstn
434
435
436
437
438 
            refclk
439
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441 
            refclk
442
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444
445
446 
            rgmii_txd
447
448
449 
            rgmii_txd
450
451
452
453
454 
            rgmii_tx_ctl
455
456
457 
            rgmii_tx_ctl
458
459
460
461
462 
            rgmii_txc
463
464
465 
            rgmii_txc
466
467
468
469
470 
            rgmii_rxd
471
472
473 
            rgmii_rxd
474
475
476
477
478 
            rgmii_rx_ctl
479
480
481 
            rgmii_rx_ctl
482
483
484
485
486 
            rgmii_rxc
487
488
489 
            rgmii_rxc
490
491
492
493
494 
            inband_link_status
495
496
497 
            inband_link_status
498
499
500
501
502 
            inband_clock_speed
503
504
505 
            inband_clock_speed
506
507
508
509
510 
            inband_duplex_status
511
512
513 
            inband_duplex_status
514
515
516
517
518 
            mdio
519
520
521 
            mdio
522
523
524
525
526 
            mdc
527
528
529 
            mdc
530
531
532
533
534
535
536
537 
      s_axi
538
539 
        reg0
540 
        0
541 
        4096
542 
        32
543 
        register
544
545
546
547
548
549
550 
        xilinx_anylanguagesynthesis
551 
        Synthesis
552 
        :vivado.xilinx.com:synthesis
553 
        Verilog
554 
        tri_mode_ethernet_mac_0_fifo_block
555
556 
          xilinx_anylanguagesynthesis_view_fileset
557
558
559
560 
            viewChecksum
561 
            c149e424
562
563
564
565
566 
        xilinx_anylanguagebehavioralsimulation
567 
        Simulation
568 
        :vivado.xilinx.com:simulation
569 
        Verilog
570 
        tri_mode_ethernet_mac_0_fifo_block
571
572 
          xilinx_anylanguagebehavioralsimulation_view_fileset
573
574
575
576 
            viewChecksum
577 
            abb5b541
578
579
580
581
582 
        xilinx_xpgui
583 
        UI Layout
584 
        :vivado.xilinx.com:xgui.ui
585
586 
          xilinx_xpgui_view_fileset
587
588
589
590 
            viewChecksum
591 
            f92e9879
592
593
594
595
596 
        xilinx_utilityxitfiles
597 
        Utility XIT/TTCL
598 
        :vivado.xilinx.com:xit.util
599
600
601 
            viewChecksum
602 
            a34306f3
603
604
605
606
607 
        xilinx_softwaredriver
608 
        Software Driver
609 
        :vivado.xilinx.com:sw.driver
610
611 
          xilinx_softwaredriver_view_fileset
612
613
614
615 
            viewChecksum
616 
            884863d2
617
618
619
620
621
622
623 
        gtx_clk
624
625 
          in
626
627
628 
              std_logic
629 
              xilinx_anylanguagesynthesis
630 
              xilinx_anylanguagebehavioralsimulation
631
632
633
634
635
636 
        glbl_rstn
637
638 
          in
639
640
641 
              std_logic
642 
              xilinx_anylanguagesynthesis
643 
              xilinx_anylanguagebehavioralsimulation
644
645
646
647
648
649 
        rx_axi_rstn
650
651 
          in
652
653
654 
              std_logic
655 
              xilinx_anylanguagesynthesis
656 
              xilinx_anylanguagebehavioralsimulation
657
658
659
660
661
662 
        tx_axi_rstn
663
664 
          in
665
666
667 
              std_logic
668 
              xilinx_anylanguagesynthesis
669 
              xilinx_anylanguagebehavioralsimulation
670
671
672
673
674
675 
        refclk
676
677 
          in
678
679
680 
              std_logic
681 
              xilinx_anylanguagesynthesis
682 
              xilinx_anylanguagebehavioralsimulation
683
684
685
686
687
688 
        rx_fifo_clock
689
690 
          in
691
692
693 
              std_logic
694 
              xilinx_anylanguagesynthesis
695 
              xilinx_anylanguagebehavioralsimulation
696
697
698
699
700
701 
        rx_fifo_resetn
702
703 
          in
704
705
706 
              std_logic
707 
              xilinx_anylanguagesynthesis
708 
              xilinx_anylanguagebehavioralsimulation
709
710
711
712
713
714 
        rx_axis_fifo_tdata
715
716 
          out
717
718 
            7
719 
            0
720
721
722
723 
              std_logic_vector
724 
              xilinx_anylanguagesynthesis
725 
              xilinx_anylanguagebehavioralsimulation
726
727
728
729
730
731 
        rx_axis_fifo_tvalid
732
733 
          out
734
735
736 
              std_logic
737 
              xilinx_anylanguagesynthesis
738 
              xilinx_anylanguagebehavioralsimulation
739
740
741
742
743
744 
        rx_axis_fifo_tready
745
746 
          in
747
748
749 
              std_logic
750 
              xilinx_anylanguagesynthesis
751 
              xilinx_anylanguagebehavioralsimulation
752
753
754
755
756
757 
        rx_axis_fifo_tlast
758
759 
          out
760
761
762 
              std_logic
763 
              xilinx_anylanguagesynthesis
764 
              xilinx_anylanguagebehavioralsimulation
765
766
767
768
769
770 
        tx_fifo_clock
771
772 
          in
773
774
775 
              std_logic
776 
              xilinx_anylanguagesynthesis
777 
              xilinx_anylanguagebehavioralsimulation
778
779
780
781
782
783 
        tx_fifo_resetn
784
785 
          in
786
787
788 
              std_logic
789 
              xilinx_anylanguagesynthesis
790 
              xilinx_anylanguagebehavioralsimulation
791
792
793
794
795
796 
        tx_axis_fifo_tdata
797
798 
          in
799
800 
            7
801 
            0
802
803
804
805 
              std_logic_vector
806 
              xilinx_anylanguagesynthesis
807 
              xilinx_anylanguagebehavioralsimulation
808
809
810
811
812
813 
        tx_axis_fifo_tvalid
814
815 
          in
816
817
818 
              std_logic
819 
              xilinx_anylanguagesynthesis
820 
              xilinx_anylanguagebehavioralsimulation
821
822
823
824
825
826 
        tx_axis_fifo_tready
827
828 
          out
829
830
831 
              std_logic
832 
              xilinx_anylanguagesynthesis
833 
              xilinx_anylanguagebehavioralsimulation
834
835
836
837
838
839 
        tx_axis_fifo_tlast
840
841 
          in
842
843
844 
              std_logic
845 
              xilinx_anylanguagesynthesis
846 
              xilinx_anylanguagebehavioralsimulation
847
848
849
850
851
852 
        rgmii_txd
853
854 
          out
855
856 
            3
857 
            0
858
859
860
861 
              std_logic_vector
862 
              xilinx_anylanguagesynthesis
863 
              xilinx_anylanguagebehavioralsimulation
864
865
866
867
868
869 
        rgmii_tx_ctl
870
871 
          out
872
873
874 
              std_logic
875 
              xilinx_anylanguagesynthesis
876 
              xilinx_anylanguagebehavioralsimulation
877
878
879
880
881
882 
        rgmii_txc
883
884 
          out
885
886
887 
              std_logic
888 
              xilinx_anylanguagesynthesis
889 
              xilinx_anylanguagebehavioralsimulation
890
891
892
893
894
895 
        rgmii_rxd
896
897 
          in
898
899 
            3
900 
            0
901
902
903
904 
              std_logic_vector
905 
              xilinx_anylanguagesynthesis
906 
              xilinx_anylanguagebehavioralsimulation
907
908
909
910
911
912 
        rgmii_rx_ctl
913
914 
          in
915
916
917 
              std_logic
918 
              xilinx_anylanguagesynthesis
919 
              xilinx_anylanguagebehavioralsimulation
920
921
922
923
924
925 
        rgmii_rxc
926
927 
          in
928
929
930 
              std_logic
931 
              xilinx_anylanguagesynthesis
932 
              xilinx_anylanguagebehavioralsimulation
933
934
935
936
937
938 
        inband_link_status
939
940 
          out
941
942
943 
              std_logic
944 
              xilinx_anylanguagesynthesis
945 
              xilinx_anylanguagebehavioralsimulation
946
947
948
949
950
951 
        inband_clock_speed
952
953 
          out
954
955 
            1
956 
            0
957
958
959
960 
              std_logic_vector
961 
              xilinx_anylanguagesynthesis
962 
              xilinx_anylanguagebehavioralsimulation
963
964
965
966
967
968 
        inband_duplex_status
969
970 
          out
971
972
973 
              std_logic
974 
              xilinx_anylanguagesynthesis
975 
              xilinx_anylanguagebehavioralsimulation
976
977
978
979
980
981 
        mdio
982
983 
          inout
984
985
986 
              std_logic
987 
              xilinx_anylanguagesynthesis
988 
              xilinx_anylanguagebehavioralsimulation
989
990
991
992
993
994 
        mdc
995
996 
          out
997
998
999 
              std_logic
1000 
              xilinx_anylanguagesynthesis
1001 
              xilinx_anylanguagebehavioralsimulation
1002
1003
1004
1005
1006
1007 
        s_axi_aclk
1008
1009 
          in
1010
1011
1012 
              std_logic
1013 
              xilinx_anylanguagesynthesis
1014 
              xilinx_anylanguagebehavioralsimulation
1015
1016
1017
1018
1019
1020 
        s_axi_resetn
1021
1022 
          in
1023
1024
1025 
              std_logic
1026 
              xilinx_anylanguagesynthesis
1027 
              xilinx_anylanguagebehavioralsimulation
1028
1029
1030
1031
1032
1033 
        s_axi_awaddr
1034
1035 
          in
1036
1037 
            11
1038 
            0
1039
1040
1041
1042 
              std_logic_vector
1043 
              xilinx_anylanguagesynthesis
1044 
              xilinx_anylanguagebehavioralsimulation
1045
1046
1047
1048 
            0
1049
1050
1051
1052
1053 
        s_axi_awvalid
1054
1055 
          in
1056
1057
1058 
              std_logic
1059 
              xilinx_anylanguagesynthesis
1060 
              xilinx_anylanguagebehavioralsimulation
1061
1062
1063
1064 
            0
1065
1066
1067
1068
1069 
        s_axi_awready
1070
1071 
          out
1072
1073
1074 
              std_logic
1075 
              xilinx_anylanguagesynthesis
1076 
              xilinx_anylanguagebehavioralsimulation
1077
1078
1079
1080
1081
1082 
        s_axi_wdata
1083
1084 
          in
1085
1086 
            31
1087 
            0
1088
1089
1090
1091 
              std_logic_vector
1092 
              xilinx_anylanguagesynthesis
1093 
              xilinx_anylanguagebehavioralsimulation
1094
1095
1096
1097 
            0
1098
1099
1100
1101
1102 
        s_axi_wvalid
1103
1104 
          in
1105
1106
1107 
              std_logic
1108 
              xilinx_anylanguagesynthesis
1109 
              xilinx_anylanguagebehavioralsimulation
1110
1111
1112
1113 
            0
1114
1115
1116
1117
1118 
        s_axi_wready
1119
1120 
          out
1121
1122
1123 
              std_logic
1124 
              xilinx_anylanguagesynthesis
1125 
              xilinx_anylanguagebehavioralsimulation
1126
1127
1128
1129
1130
1131 
        s_axi_bresp
1132
1133 
          out
1134
1135 
            1
1136 
            0
1137
1138
1139
1140 
              std_logic_vector
1141 
              xilinx_anylanguagesynthesis
1142 
              xilinx_anylanguagebehavioralsimulation
1143
1144
1145
1146
1147
1148 
        s_axi_bvalid
1149
1150 
          out
1151
1152
1153 
              std_logic
1154 
              xilinx_anylanguagesynthesis
1155 
              xilinx_anylanguagebehavioralsimulation
1156
1157
1158
1159
1160
1161 
        s_axi_bready
1162
1163 
          in
1164
1165
1166 
              std_logic
1167 
              xilinx_anylanguagesynthesis
1168 
              xilinx_anylanguagebehavioralsimulation
1169
1170
1171
1172 
            0
1173
1174
1175
1176
1177 
        s_axi_araddr
1178
1179 
          in
1180
1181 
            11
1182 
            0
1183
1184
1185
1186 
              std_logic_vector
1187 
              xilinx_anylanguagesynthesis
1188 
              xilinx_anylanguagebehavioralsimulation
1189
1190
1191
1192 
            0
1193
1194
1195
1196
1197 
        s_axi_arvalid
1198
1199 
          in
1200
1201
1202 
              std_logic
1203 
              xilinx_anylanguagesynthesis
1204 
              xilinx_anylanguagebehavioralsimulation
1205
1206
1207
1208 
            0
1209
1210
1211
1212
1213 
        s_axi_arready
1214
1215 
          out
1216
1217
1218 
              std_logic
1219 
              xilinx_anylanguagesynthesis
1220 
              xilinx_anylanguagebehavioralsimulation
1221
1222
1223
1224
1225
1226 
        s_axi_rdata
1227
1228 
          out
1229
1230 
            31
1231 
            0
1232
1233
1234
1235 
              std_logic_vector
1236 
              xilinx_anylanguagesynthesis
1237 
              xilinx_anylanguagebehavioralsimulation
1238
1239
1240
1241
1242
1243 
        s_axi_rresp
1244
1245 
          out
1246
1247 
            1
1248 
            0
1249
1250
1251
1252 
              std_logic_vector
1253 
              xilinx_anylanguagesynthesis
1254 
              xilinx_anylanguagebehavioralsimulation
1255
1256
1257
1258
1259
1260 
        s_axi_rvalid
1261
1262 
          out
1263
1264
1265 
              std_logic
1266 
              xilinx_anylanguagesynthesis
1267 
              xilinx_anylanguagebehavioralsimulation
1268
1269
1270
1271
1272
1273 
        s_axi_rready
1274
1275 
          in
1276
1277
1278 
              std_logic
1279 
              xilinx_anylanguagesynthesis
1280 
              xilinx_anylanguagebehavioralsimulation
1281
1282
1283
1284 
            0
1285
1286
1287
1288
1289
1290
1291
1292 
      choice_list_9d8b0d81
1293 
      ACTIVE_HIGH
1294 
      ACTIVE_LOW
1295
1296
1297
1298
1299 
      xilinx_anylanguagesynthesis_view_fileset
1300
1301 
        src/tri_mode_ethernet_mac_0_fifo_block.v
1302 
        verilogSource
1303 
        CHECKSUM_dc5d0cc0
1304
1305
1306 
        src/common/tri_mode_ethernet_mac_0_reset_sync.v
1307 
        verilogSource
1308
1309
1310 
        src/common/tri_mode_ethernet_mac_0_sync_block.v
1311 
        verilogSource
1312
1313
1314 
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1347
1348 
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