Subversion Repositories 1g_ethernet_dpi

//------------------------------------------------------------------------------

// File       : tri_mode_ethernet_mac_0_example_design_resets.v

// Author     : Xilinx Inc.

// -----------------------------------------------------------------------------

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// -----------------------------------------------------------------------------

// Description:  This block generates fully synchronous resets for each clock domain

`timescale 1 ps/1 ps

module tri_mode_ethernet_mac_0_example_design_resets

   (

   // clocks

   input          s_axi_aclk,

   input          gtx_clk,

   // asynchronous resets

   input          glbl_rst,

   input          reset_error,

   input          rx_reset,

   input          tx_reset,

   input          dcm_locked,

   // synchronous reset outputs

   output         glbl_rst_intn,

   output   reg   gtx_resetn = 0,

   output   reg   s_axi_resetn = 0,

   output         phy_resetn,

   output   reg   chk_resetn = 0

   );

// define internal signals

    reg           s_axi_pre_resetn = 0;

    wire          s_axi_reset_int;

    reg           gtx_pre_resetn = 0;

    wire          gtx_clk_reset_int;

    reg           chk_pre_resetn = 0;

    wire          chk_reset_int;

    wire          dcm_locked_sync;

    reg           phy_resetn_int;

    reg  [5:0]    phy_reset_count;

  //----------------------------------------------------------------------------

  // Synchronise the async dcm_locked into the gtx_clk clock domain

  //----------------------------------------------------------------------------

  tri_mode_ethernet_mac_0_sync_block dcm_sync (

     .clk              (gtx_clk),

     .data_in          (dcm_locked),

     .data_out         (dcm_locked_sync)

  );

  //----------------------------------------------------------------------------

  // Generate resets required for the fifo side signals etc

  //----------------------------------------------------------------------------

  // in each case the async reset is first captured and then synchronised

  //---------------

  // global reset

   tri_mode_ethernet_mac_0_reset_sync glbl_reset_gen (

      .clk              (gtx_clk),

      .enable           (dcm_locked_sync),

      .reset_in         (glbl_rst),

      .reset_out        (glbl_rst_int)

   );

   assign glbl_rst_intn = !glbl_rst_int;

  //---------------

  // AXI-Lite reset

   tri_mode_ethernet_mac_0_reset_sync axi_lite_reset_gen (

      .clk              (s_axi_aclk),

      .enable           (phy_resetn_int),

      .reset_in         (glbl_rst),

      .reset_out        (s_axi_reset_int)

   );

   // Create fully synchronous reset in the s_axi clock domain.

   always @(posedge s_axi_aclk)

   begin

     if (s_axi_reset_int) begin

       s_axi_pre_resetn <= 0;

       s_axi_resetn     <= 0;

     end

     else begin

       s_axi_pre_resetn <= 1;

       s_axi_resetn     <= s_axi_pre_resetn;

     end

   end

  //---------------

  // gtx_clk reset

   tri_mode_ethernet_mac_0_reset_sync gtx_reset_gen (

      .clk              (gtx_clk),

      .enable           (dcm_locked_sync),

      .reset_in         (glbl_rst || rx_reset || tx_reset),

      .reset_out        (gtx_clk_reset_int)

   );

   // Create fully synchronous reset in the gtx_clk domain.

   always @(posedge gtx_clk)

   begin

     if (gtx_clk_reset_int) begin

       gtx_pre_resetn  <= 0;

       gtx_resetn      <= 0;

     end

     else begin

       gtx_pre_resetn  <= 1;

       gtx_resetn      <= gtx_pre_resetn;

     end

   end

  //---------------

  // data check reset

   tri_mode_ethernet_mac_0_reset_sync chk_reset_gen (

      .clk              (gtx_clk),

      .enable           (dcm_locked_sync),

      .reset_in         (glbl_rst || reset_error),

      .reset_out        (chk_reset_int)

   );

   // Create fully synchronous reset in the gtx_clk domain.

   always @(posedge gtx_clk)

   begin

     if (chk_reset_int) begin

       chk_pre_resetn  <= 0;

       chk_resetn      <= 0;

     end

     else begin

       chk_pre_resetn  <= 1;

       chk_resetn      <= chk_pre_resetn;

     end

   end

   //---------------

   // PHY reset

   // the phy reset output (active low) needs to be held for at least 10x25MHZ cycles

   // this is derived using the 125MHz available and a 6 bit counter

   always @(posedge gtx_clk)

   begin

      if (glbl_rst_int) begin

         phy_resetn_int <= 0;

         phy_reset_count <= 0;

      end

      else begin

         if (!(&phy_reset_count)) begin

            phy_reset_count <= phy_reset_count + 1;

         end

         else begin

            phy_resetn_int <= 1;

         end

      end

   end

   assign phy_resetn = phy_resetn_int;

endmodule