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[/] [2d_game_console/] [trunk/] [Processor_ModelSim/] [Memory_Arbiter.v] - Blame information for rev 2

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module Memory_Arbiter(
 
clock,
reset,
 
addr_7,
data_7,
wren_7,
req_7,
 
addr_6,
data_6,
wren_6,
req_6,
 
addr_5,
data_5,
wren_5,
req_5,
 
addr_4,
data_4,
wren_4,
req_4,
 
addr_3,
data_3,
wren_3,
req_3,
 
addr_2,
data_2,
wren_2,
req_2,
 
addr_1,
data_1,
wren_1,
req_1,
 
addr_0,
data_0,
wren_0,
req_0,
 
 
grant_7,
grant_6,
grant_5,
grant_4,
grant_3,
grant_2,
grant_1,
grant_0,
 
addr,
data,
wren,
 
current_state,
next_state
 
 
);
 
 
input           [15:0]   addr_0;
input           [15:0]   addr_1;
input           [15:0]   addr_2;
input           [15:0]   addr_3;
input           [15:0]   addr_4;
input           [15:0]   addr_5;
input           [15:0]   addr_6;
input           [15:0]   addr_7;
 
input           [15:0]   data_0;
input           [15:0]   data_1;
input           [15:0]   data_2;
input           [15:0]   data_3;
input           [15:0]   data_4;
input           [15:0]   data_5;
input           [15:0]   data_6;
input           [15:0]   data_7;
 
input           wren_0;
input           wren_1;
input           wren_2;
input           wren_3;
input           wren_4;
input           wren_5;
input           wren_6;
input           wren_7;
 
input           req_0;
input           req_1;
input           req_2;
input           req_3;
input           req_4;
input           req_5;
input           req_6;
input           req_7;
 
input   clock;
input   reset;
 
 
output reg      [15:0]   addr;
output reg      [15:0]   data;
output reg                              wren;
 
output reg                              grant_0;
output reg                              grant_1;
output reg                              grant_2;
output reg                              grant_3;
output reg                              grant_4;
output reg                              grant_5;
output reg                              grant_6;
output reg                              grant_7;
 
 
/*########################################################################*/
/*########################  FINITE STATE MACHINE  ########################*/
/*########################  MEMORY ARBITER        ########################*/
/*########################################################################*/
 
output reg      [3:0]            current_state;
output reg      [3:0]            next_state;
 
// States
parameter       Idle            = 4'b0000;      // Idle         = 0
parameter       Grant_0 = 4'b0001;      // Grant_0      = 1
parameter       Grant_1 = 4'b0010;      // Grant_1      = 2
parameter       Grant_2 = 4'b0011;      // Grant_2      = 3
parameter       Grant_3 = 4'b0100;      // Grant_3      = 4
parameter       Grant_4 = 4'b0101;      // Grant_4      = 5
parameter       Grant_5 = 4'b0110;      // Grant_5      = 6
parameter       Grant_6 = 4'b0111;      // Grant_6      = 7
parameter       Grant_7 = 4'b1000;      // Grant_7      = 8
 
// Next State Decoder
always @ (*)
begin
        case (current_state)
 
                // State 0
                Idle:
                begin
                        if (req_0)
                                next_state = Grant_0;
 
                        else if (req_1)
                                next_state = Grant_1;
 
                        else if (req_2)
                                next_state = Grant_2;
 
                        else if (req_3)
                                next_state = Grant_3;
 
                        else if (req_4)
                                next_state = Grant_4;
 
                        else if (req_5)
                                next_state = Grant_5;
 
                        else if (req_6)
                                next_state = Grant_6;
 
                        else if (req_7)
                                next_state = Grant_7;
 
                        else
                                next_state = Idle;
                end
 
                // State 1
                Grant_0:
                begin
                        if (req_0)
                                next_state = Grant_0;
                        else
                                next_state = Idle;
                end
 
                // State 2
                Grant_1:
                begin
                        if (req_1)
                                next_state = Grant_1;
                        else
                                next_state = Idle;
                end
 
                // State 3
                Grant_2:
                begin
                        if (req_2)
                                next_state = Grant_2;
                        else
                                next_state = Idle;
                end
 
                // State 4
                Grant_3:
                begin
                        if (req_3)
                                next_state = Grant_3;
                        else
                                next_state = Idle;
                end
 
                // State 5
                Grant_4:
                begin
                        if (req_4)
                                next_state = Grant_4;
                        else
                                next_state = Idle;
                end
 
                // State 6
                Grant_5:
                begin
                        if (req_5)
                                next_state = Grant_5;
                        else
                                next_state = Idle;
                end
 
                // State 7
                Grant_6:
                begin
                        if (req_6)
                                next_state = Grant_6;
                        else
                                next_state = Idle;
                end
 
                // State 8
                Grant_7:
                begin
                        if (req_7)
                                next_state = Grant_7;
                        else
                                next_state = Idle;
                end
 
                default:
                begin
                        next_state = Idle;
                end
 
        endcase
 
end
 
 
// Output Decoder
always @ (*)
begin
 
        // Default Assignments
        addr = addr_0;
        data = data_0;
        wren = 0;
        grant_0 = 0;
        grant_1 = 0;
        grant_2 = 0;
        grant_3 = 0;
        grant_4 = 0;
        grant_5 = 0;
        grant_6 = 0;
        grant_7 = 0;
 
 
        case (current_state)
 
                // State 0
                Idle:
                begin
 
                end
 
                // State 1
                Grant_0:
                begin
                        addr = addr_0;
                        data = data_0;
                        wren = wren_0;
                        grant_0 = 1;
                end
 
                // State 2
                Grant_1:
                begin
                        addr = addr_1;
                        data = data_1;
                        wren = wren_1;
                        grant_1 = 1;
                end
 
                // State 3
                Grant_2:
                begin
                        addr = addr_2;
                        data = data_2;
                        wren = wren_2;
                        grant_2 = 1;
                end
 
                // State 4
                Grant_3:
                begin
                        addr = addr_3;
                        data = data_3;
                        wren = wren_3;
                        grant_3 = 1;
                end
 
                // State 5
                Grant_4:
                begin
                        addr = addr_4;
                        data = data_4;
                        wren = wren_4;
                        grant_4 = 1;
                end
 
                // State 6
                Grant_5:
                begin
                        addr = addr_5;
                        data = data_5;
                        wren = wren_5;
                        grant_5 = 1;
                end
 
                // State 7
                Grant_6:
                begin
                        addr = addr_6;
                        data = data_6;
                        wren = wren_6;
                        grant_6 = 1;
                end
 
                // State 8
                Grant_7:
                begin
                        addr = addr_7;
                        data = data_7;
                        wren = wren_7;
                        grant_7 = 1;
                end
 
                default:
                begin
 
                end
 
        endcase
end
 
 
// State Register and Reset Logic
always @ (posedge clock)
begin
 
        if (reset)
        begin
                current_state   <= Idle;
        end
 
        else
        begin
                current_state   <=      next_state;
        end
 
end
 
/*########################################################################*/
/*########################################################################*/
 
 
endmodule

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[/] [2d_game_console/] [trunk/] [Processor_ModelSim/] [Memory_Arbiter.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	lucas.vbal	`module Memory_Arbiter(`
2
3			`clock,`
4			`reset,`
5
6			`addr_7,`
7			`data_7,`
8			`wren_7,`
9			`req_7,`
10
11			`addr_6,`
12			`data_6,`
13			`wren_6,`
14			`req_6,`
15
16			`addr_5,`
17			`data_5,`
18			`wren_5,`
19			`req_5,`
20
21			`addr_4,`
22			`data_4,`
23			`wren_4,`
24			`req_4,`
25
26			`addr_3,`
27			`data_3,`
28			`wren_3,`
29			`req_3,`
30
31			`addr_2,`
32			`data_2,`
33			`wren_2,`
34			`req_2,`
35
36			`addr_1,`
37			`data_1,`
38			`wren_1,`
39			`req_1,`
40
41			`addr_0,`
42			`data_0,`
43			`wren_0,`
44			`req_0,`
45
46
47			`grant_7,`
48			`grant_6,`
49			`grant_5,`
50			`grant_4,`
51			`grant_3,`
52			`grant_2,`
53			`grant_1,`
54			`grant_0,`
55
56			`addr,`
57			`data,`
58			`wren,`
59
60			`current_state,`
61			`next_state`
62
63
64			`);`
65
66
67			`input [15:0] addr_0;`
68			`input [15:0] addr_1;`
69			`input [15:0] addr_2;`
70			`input [15:0] addr_3;`
71			`input [15:0] addr_4;`
72			`input [15:0] addr_5;`
73			`input [15:0] addr_6;`
74			`input [15:0] addr_7;`
75
76			`input [15:0] data_0;`
77			`input [15:0] data_1;`
78			`input [15:0] data_2;`
79			`input [15:0] data_3;`
80			`input [15:0] data_4;`
81			`input [15:0] data_5;`
82			`input [15:0] data_6;`
83			`input [15:0] data_7;`
84
85			`input wren_0;`
86			`input wren_1;`
87			`input wren_2;`
88			`input wren_3;`
89			`input wren_4;`
90			`input wren_5;`
91			`input wren_6;`
92			`input wren_7;`
93
94			`input req_0;`
95			`input req_1;`
96			`input req_2;`
97			`input req_3;`
98			`input req_4;`
99			`input req_5;`
100			`input req_6;`
101			`input req_7;`
102
103			`input clock;`
104			`input reset;`
105
106
107			`output reg [15:0] addr;`
108			`output reg [15:0] data;`
109			`output reg wren;`
110
111			`output reg grant_0;`
112			`output reg grant_1;`
113			`output reg grant_2;`
114			`output reg grant_3;`
115			`output reg grant_4;`
116			`output reg grant_5;`
117			`output reg grant_6;`
118			`output reg grant_7;`
119
120
121			`/########################################################################/`
122			`/######################## FINITE STATE MACHINE ########################/`
123			`/######################## MEMORY ARBITER ########################/`
124			`/########################################################################/`
125
126			`output reg [3:0] current_state;`
127			`output reg [3:0] next_state;`
128
129			`// States`
130			`parameter Idle = 4'b0000; // Idle = 0`
131			`parameter Grant_0 = 4'b0001; // Grant_0 = 1`
132			`parameter Grant_1 = 4'b0010; // Grant_1 = 2`
133			`parameter Grant_2 = 4'b0011; // Grant_2 = 3`
134			`parameter Grant_3 = 4'b0100; // Grant_3 = 4`
135			`parameter Grant_4 = 4'b0101; // Grant_4 = 5`
136			`parameter Grant_5 = 4'b0110; // Grant_5 = 6`
137			`parameter Grant_6 = 4'b0111; // Grant_6 = 7`
138			`parameter Grant_7 = 4'b1000; // Grant_7 = 8`
139
140			`// Next State Decoder`
141			`always @ (*)`
142			`begin`
143			`case (current_state)`
144
145			`// State 0`
146			`Idle:`
147			`begin`
148			`if (req_0)`
149			`next_state = Grant_0;`
150
151			`else if (req_1)`
152			`next_state = Grant_1;`
153
154			`else if (req_2)`
155			`next_state = Grant_2;`
156
157			`else if (req_3)`
158			`next_state = Grant_3;`
159
160			`else if (req_4)`
161			`next_state = Grant_4;`
162
163			`else if (req_5)`
164			`next_state = Grant_5;`
165
166			`else if (req_6)`
167			`next_state = Grant_6;`
168
169			`else if (req_7)`
170			`next_state = Grant_7;`
171
172			`else`
173			`next_state = Idle;`
174			`end`
175
176			`// State 1`
177			`Grant_0:`
178			`begin`
179			`if (req_0)`
180			`next_state = Grant_0;`
181			`else`
182			`next_state = Idle;`
183			`end`
184
185			`// State 2`
186			`Grant_1:`
187			`begin`
188			`if (req_1)`
189			`next_state = Grant_1;`
190			`else`
191			`next_state = Idle;`
192			`end`
193
194			`// State 3`
195			`Grant_2:`
196			`begin`
197			`if (req_2)`
198			`next_state = Grant_2;`
199			`else`
200			`next_state = Idle;`
201			`end`
202
203			`// State 4`
204			`Grant_3:`
205			`begin`
206			`if (req_3)`
207			`next_state = Grant_3;`
208			`else`
209			`next_state = Idle;`
210			`end`
211
212			`// State 5`
213			`Grant_4:`
214			`begin`
215			`if (req_4)`
216			`next_state = Grant_4;`
217			`else`
218			`next_state = Idle;`
219			`end`
220
221			`// State 6`
222			`Grant_5:`
223			`begin`
224			`if (req_5)`
225			`next_state = Grant_5;`
226			`else`
227			`next_state = Idle;`
228			`end`
229
230			`// State 7`
231			`Grant_6:`
232			`begin`
233			`if (req_6)`
234			`next_state = Grant_6;`
235			`else`
236			`next_state = Idle;`
237			`end`
238
239			`// State 8`
240			`Grant_7:`
241			`begin`
242			`if (req_7)`
243			`next_state = Grant_7;`
244			`else`
245			`next_state = Idle;`
246			`end`
247
248			`default:`
249			`begin`
250			`next_state = Idle;`
251			`end`
252
253			`endcase`
254
255			`end`
256
257
258			`// Output Decoder`
259			`always @ (*)`
260			`begin`
261
262			`// Default Assignments`
263			`addr = addr_0;`
264			`data = data_0;`
265			`wren = 0;`
266			`grant_0 = 0;`
267			`grant_1 = 0;`
268			`grant_2 = 0;`
269			`grant_3 = 0;`
270			`grant_4 = 0;`
271			`grant_5 = 0;`
272			`grant_6 = 0;`
273			`grant_7 = 0;`
274
275
276			`case (current_state)`
277
278			`// State 0`
279			`Idle:`
280			`begin`
281
282			`end`
283
284			`// State 1`
285			`Grant_0:`
286			`begin`
287			`addr = addr_0;`
288			`data = data_0;`
289			`wren = wren_0;`
290			`grant_0 = 1;`
291			`end`
292
293			`// State 2`
294			`Grant_1:`
295			`begin`
296			`addr = addr_1;`
297			`data = data_1;`
298			`wren = wren_1;`
299			`grant_1 = 1;`
300			`end`
301
302			`// State 3`
303			`Grant_2:`
304			`begin`
305			`addr = addr_2;`
306			`data = data_2;`
307			`wren = wren_2;`
308			`grant_2 = 1;`
309			`end`
310
311			`// State 4`
312			`Grant_3:`
313			`begin`
314			`addr = addr_3;`
315			`data = data_3;`
316			`wren = wren_3;`
317			`grant_3 = 1;`
318			`end`
319
320			`// State 5`
321			`Grant_4:`
322			`begin`
323			`addr = addr_4;`
324			`data = data_4;`
325			`wren = wren_4;`
326			`grant_4 = 1;`
327			`end`
328
329			`// State 6`
330			`Grant_5:`
331			`begin`
332			`addr = addr_5;`
333			`data = data_5;`
334			`wren = wren_5;`
335			`grant_5 = 1;`
336			`end`
337
338			`// State 7`
339			`Grant_6:`
340			`begin`
341			`addr = addr_6;`
342			`data = data_6;`
343			`wren = wren_6;`
344			`grant_6 = 1;`
345			`end`
346
347			`// State 8`
348			`Grant_7:`
349			`begin`
350			`addr = addr_7;`
351			`data = data_7;`
352			`wren = wren_7;`
353			`grant_7 = 1;`
354			`end`
355
356			`default:`
357			`begin`
358
359			`end`
360
361			`endcase`
362			`end`
363
364
365			`// State Register and Reset Logic`
366			`always @ (posedge clock)`
367			`begin`
368
369			`if (reset)`
370			`begin`
371			`current_state <= Idle;`
372			`end`
373
374			`else`
375			`begin`
376			`current_state <= next_state;`
377			`end`
378
379			`end`
380
381			`/########################################################################/`
382			`/########################################################################/`
383
384
385			`endmodule`